scholarly journals A shared-cube approach to ESOP-based synthesis of reversible logic

2011 ◽  
Vol 24 (3) ◽  
pp. 385-402 ◽  
Author(s):  
Noor Nayeem ◽  
Jacqueline Rice
Keyword(s):  
Power Loss ◽  
Heat Dissipation ◽  
Logic Synthesis ◽  
Reversible Logic ◽  
Experimental Results ◽  
Quantum Cost ◽  
Toffoli Gate ◽  
Gate Count ◽  
Computing Industry ◽  
Synthesis Approach

Reversible logic is being suggested as a possibility for overcoming potential power loss and heat dissipation problems that the computing industry may soon be at a loss to overcome. However, for reversible logic to be a solution we must have techniques for synthesizing function descriptions to reversible circuits. This paper presents an improved ESOP-based reversible logic synthesis approach which leverages situations where cubes are shared by multiple outputs and ensures that the implementation of each cube requires just one Toffoli gate. It has the potential to minimize both gate count and quantum cost, and in fact our experimental results show that this technique can reduce the quantum cost up to 75% compared to results from the existing work.

Estimation of Power for Reversible Subtractors

2018 ◽  
Vol 7 (4.5) ◽  
pp. 102
Author(s):  
E. V.Naga Lakshmi ◽  
Dr. N.Siva Sankara Reddy
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Logic Gates ◽  
Logic Circuits ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Gate Count ◽  
Garbage Output ◽  
Reversible Logic Gates

In recent years Reversible Logic Circuits (RLC) are proved to be more efficient in terms of power dissipation. Hence, most of the researchers developed Reversible logic circuits for low power applications. RLC are designed with the help of Reversible Logic Gates (RLG).   Efficiency of the Reversible gates is measured in terms of Quantum cost, gate count, garbage output lines, logic depth and constant inputs. In this paper, measurement of power for RLG is done. Basic RLGs are designed using GDI technology and compared in terms of power dissipation. 1 bit Full subtractor is designed using EVNL gate [1] and also with TG& Fy [6] gates. The power dissipation is compared with 1 bit TR gate [5] full subtractor.  Then 2 bit, 4 bit and 8 bit subtractors are designed and compared the powers. Proposed 4 bit and 8 bit full subtractors are dissipating less power when compared to TR gate 4 bit and 8 bit subtractors.  

A Novel Approach to Design a 4-Bit Binary Comparator Circuit with Reversible Logic using CDSM Gate

2015 ◽  
Vol 11 (1) ◽  
pp. 36-49
Author(s):  
Vandana Shukla ◽  
O. P. Singh ◽  
G. R. Mishra ◽  
R. K. Tiwari
Keyword(s):  
Low Power ◽  
Power Loss ◽  
Optical Computing ◽  
Logic Gates ◽  
Digital Circuit ◽  
Reversible Logic ◽  
Processing Unit ◽  
Quantum Cost ◽  
Central Processing ◽  
Control Circuits

In the recent scenario of microelectronic industry, the reversible logic is considered as the burgeonic technology for digital circuit designing. It deals with the aim to generate digital circuits with zero power loss characteristics. Optical computing, Nanotechnology, Low power CMOS design and Digital Signal Processing (DSP) processors are leading areas of development with the concept of reversible logic. Researchers have already proposed various subsystems of the computer for the creation of low power loss devices with the help of numerous available reversible logic gates. Here in this paper, the authors have proposed a new reversible gate named as CDSM gate with 4×4 size. This CDSM gate is used to design optimized 4-bit binary comparator. The optimization is improved as compared to the existing designs based on some significant performance parameters such as total number of gates, garbage outputs generated, constant inputs and quantum cost. Comparators are widely used in various computing applications such as counters, convertor, Central Processing Unit (CPU) and control circuits etc. The comparator circuits using reversible logic can be visualized as a low power loss subsystem for the development of improved digital systems.

Efficient designs of reversible BCD to EX-3 Converter with low quantum cost in nanoscale

2020 ◽  
Vol 18 (05) ◽  
pp. 2050020 ◽  
Author(s):  
Mojtaba Noorallahzadeh ◽  
Mohammad Mosleh
Keyword(s):  
Quantum Computing ◽  
Optical Computing ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Computing Systems ◽  
Gate Count ◽  
Reversible Gate ◽  
Significant Research ◽  
Research Domain ◽  
Better Than

As an interesting and significant research domain, reversible logic is massively utilized in technologies, including optical computing, cryptography, quantum computing, nanotechnology, and so on. The realization of quantum computing is not possible without the implementation of reversible logic, and reversible designs are presented mainly to minimize the thermal loss because of the data input bits lost in the irreversible circuit. Digital converters, as the most important logic circuits, are used to connect computing systems with different binary codes. This paper first proposes a new reversible gate called Reversible Noorallahzadeh[Formula: see text]Mosleh Gate (RNMG). Then, using the proposed RNMG gate as well as existing NMG1, NMG6, and PG gates, three different designs of reversible Binary-Coded Decimal (BCD) to EX-3 code converter are proposed. Our results indicate that the proposed BCD to EX-3 code converters are superior to previous designs in terms of quantum cost. Moreover, the proposed converters are comparable or better than previous designs in terms of gate count, constant inputs, and garbage outputs.

Novel design of multiplexer and demultiplexer using reversible logic gates

2018 ◽  
Vol 7 (3.29) ◽  
pp. 80
Author(s):  
Veerendra Nath Nune ◽  
Addanki Purna R
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Logic Gates ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Gate Count ◽  
Reversible Logic Gates ◽  
Novel Design

Reversibility is the prominent technology in the recent era. In reversible logic the number output lines are equal to the number of input lines. In reversible logic the inputs are to be retrieved from the outputs. Reversible logic gates are user defined gates. Reversible logic owns its applications in various fields which include low power VLSI. In this paper multiplexer is implemented using QCA, SAM and QCA & SAM gate. Also demultiplexer is implemented using two new reversible logic gates RAMESH and RAMESH-1 gates. These designs are simulated and synthesized using Xilinx ISE 12.1 and Mentor Graphics tool. The result shows that the proposed designs are more efficient in terms of gate count, quantum cost and power consumption.  

scholarly journals FPGA Implementation of Encryption and Decryption of a Message using Optimized Reconfigurable Reversible Gate

2019 ◽  
Vol 8 (2) ◽  
pp. 1654-1658
Keyword(s):  
Power Dissipation ◽  
Heat Dissipation ◽  
Synthesis Process ◽  
Toffoli Gate ◽  
Reversible Computation ◽  
Reversible Computing ◽  
Gate Count ◽  
Reversible Gate ◽  
Encryption And Decryption ◽  
Encryption Decryption

The prime incentive to learn reversible computation is that it is the best efficient way to reduce heat dissipation than any other conventional methods. The major condition for reversibility is that there is a one-to-one connection between each input and output vectors and it has received a huge significance because of there no information loss throughout the reversible computation which results in reduces the power dissipation. Here, we proposed the design of encryption/decryption of the data schemes by using reversible computing. In this regard, a basic building block is designed for encryption design is simply cascading of a 4-bit reversible gates and it is performed every 4-variable reversible functions, for this intention a new reconfigurable reversible gate (RRG) is proposed and is designed with the use of basic reversible gates like NOT gate, CNOT gate, Toffoli gate, and Fredkin gates. In this work, the encryption/decryption of an 8-bit data is proposed and the Simulation results of encryption/decryption of the circuits using reversible gates are also presented. The gate count, delay, constant inputs, and the garbage outputs are calculated. The complete Simulation and the synthesis process can be finished with the Xilinx ISE 14.7 version and it is dumped on the FPGA Zynq board.

A Cycle Based Reversible Logic Synthesis Approach

2013 ◽  
Author(s):  
Kamalika Datta ◽  
Bhadreswar Ghuku ◽  
Devi Sandeep ◽  
Indranil Sengupta ◽  
Hafizur Rahaman
Keyword(s):  
Logic Synthesis ◽  
Reversible Logic ◽  
Synthesis Approach ◽  
Reversible Logic Synthesis

Improved Ternary Reversible Logic Synthesis Using Group Theoretic Approach

2020 ◽  
Vol 29 (12) ◽  
pp. 2050192 ◽  
Author(s):  
P. Mercy Nesa Rani ◽  
Kamalika Datta
Keyword(s):  
Binary Systems ◽  
Logic Synthesis ◽  
Quantum Systems ◽  
Theoretic Approach ◽  
Quantum Cost ◽  
Decomposition Approach ◽  
Gate Count ◽  
Higher Dimensional ◽  
Significant Attention ◽  
Computing Element

Quantum computation relies on exploiting quantum mechanical phenomena, and has received significant attention in recent years. Higher-dimensional quantum systems increase the density of encoded information per computing element (e.g., qutrit for three-level system), resulting in less resource overhead. For instance, 63% reduction in the number of qutrits is possible for ternary quantum systems as compared to the corresponding binary systems. The proposed work exploits this fact to synthesize ternary reversible circuits employing a cycle-based technique. The method starts from the ternary reversible specification of a given function in the form of a permutation. The permutation cycles are factored into simpler three-cycles and two-cycles, which are then mapped to ternary reversible gates. Different gate libraries are used to synthesize three-cycles and two-cycles, respectively. A gate decomposition approach is also proposed to synthesize a quantum gate netlist in terms of elementary ternary quantum gates, viz. Muthukrishnan–Stroud gate and shift gate. Synthesis results on benchmark functions indicate that the proposed method results in 27% and 6% improvements in quantum cost and gate count, respectively, over existing works in the literature.

Performance Analysis of Reversible Finite Field Arithmetic Architectures Over GF(p) and GF(2m) in Elliptic Curve Cryptography

2015 ◽  
Vol 24 (08) ◽  
pp. 1550122 ◽  
Author(s):  
P. Saravanan ◽  
P. Kalpana
Keyword(s):  
Elliptic Curve ◽  
Power Analysis ◽  
Performance Metrics ◽  
Logic Synthesis ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Public Key Cryptosystems ◽  
Elliptic Curve Cryptosystems ◽  
Hardware Architectures ◽  
Key Length

Elliptic curve cryptosystems (ECC) are becoming more and more popular and are included in many standards, as they offer high security strength when compared with other conventional public-key cryptosystems, for the same key length. But the security strength of hardware implementations of ECC is challenged by side channel attacks (SCA) such as power analysis. Reversible logic circuits ideally consume zero energy, which serves as the motivation to implement cryptographic algorithms against power analysis attacks. This paper proposes two new hardware architectures for performing montgomery multiplication in GF(p) and GF(2m), as they are the power consuming operations in ECC. The two architectures are optimized to reduce the hardware cost and they are then implemented in reversible logic with reduced number of quantum cost. In this work, the reversible logic synthesis is performed with Toffoli family of reversible gates. The performance metrics of all the multipliers are analyzed and properly tabulated. Scalar multiplication on elliptic curve points, which is the core operation used in every elliptic curve cryptosystem, has been implemented in reversible logic by using the proposed reversible montgomery multipliers.

scholarly journals Reversible logic synthesis by quantum rotation gates

2013 ◽  
Vol 13 (9&10) ◽  
pp. 771-792
Author(s):  
Afshin Abdollahi ◽  
Mehdi Saeedi ◽  
Massoud Pedram
Keyword(s):  
Logic Synthesis ◽  
Canonical Representation ◽  
Reversible Logic ◽  
Boolean Logic ◽  
Decision Diagrams ◽  
Multiple Control ◽  
Decomposition Approach ◽  
Binary Decision ◽  
Gate Count ◽  
Toffoli Gates

A rotation-based synthesis framework for reversible logic is proposed. We develop a canonical representation based on binary decision diagrams and introduce operators to manipulate the developed representation model. Furthermore, a recursive functional bi-decomposition approach is proposed to automatically synthesize a given function. While Boolean reversible logic is particularly addressed, our framework constructs intermediate quantum states that may be in superposition, hence we combine techniques from reversible Boolean logic and quantum computation. {The proposed approach results in quadratic gate count for multiple-control Toffoli gates without ancillae, linear depth for quantum carry-ripple adder, and $O(n\log^2 n)$ size for quantum multiplexer.

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