Characterization of Soft Error Rate Against Memory Elements Spacing and Clock Skew in a Logic with Triple Modular Redundancy in a 65nm Process
Keyword(s):
2000 ◽
Vol 35
(10)
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pp. 1422-1429
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2012 ◽
Vol 59
(6)
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pp. 2914-2919
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Keyword(s):
Keyword(s):
1983 ◽
Vol 4
(6)
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pp. 172-174
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