Charm mixing and CPV violation at LHCb experiment

The ring imaging Cherenkov detectors of the LHCb experiment

Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment ◽

10.1016/j.nima.2010.09.158 ◽

2011 ◽

Vol 639 (1) ◽

pp. 11-14 ◽

Cited By ~ 7

Author(s):

F. Muheim

Keyword(s):

Cherenkov Detectors ◽

Lhcb Experiment ◽

Ring Imaging

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An integrated control system for the LHCb experiment

2009 16th IEEE-NPSS Real Time Conference ◽

10.1109/rtc.2009.5322168 ◽

2009 ◽

Cited By ~ 1

Author(s):

A. Sambade ◽

F. Alessio ◽

C. Barandela ◽

O. Callot ◽

M. Frank ◽

...

Keyword(s):

Control System ◽

Integrated Control ◽

Lhcb Experiment ◽

Integrated Control System

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The LHCb vertex locator upgrade — the detector calibration overview

Journal of Instrumentation ◽

10.1088/1748-0221/17/01/c01046 ◽

2022 ◽

Vol 17 (01) ◽

pp. C01046

Author(s):

P. Kopciewicz ◽

S. Maccolini ◽

T. Szumlak

Keyword(s):

Large Hadron Collider ◽

Cp Violation ◽

Hadron Collider ◽

Data Rate ◽

Readout System ◽

Output Data ◽

Detector Calibration ◽

Lhcb Experiment ◽

Tracking Detector ◽

Tracking Technology

Abstract The Vertex Locator (VELO) is a silicon tracking detector in the spectrometer of the Large Hadron Collider beauty (LHCb) experiment. LHCb explores and investigates CP violation phenomena in b- and c- hadron decays and is one of the experiments operating on the Large Hadron Collider (LHC) at CERN. After run 1 and run 2 of LHC data taking (2011–2018), the LHCb detectors are being modernized within the LHCb upgrade I program. The upgrade aims to adjust the spectrometer to readout at full LHC 40 MHz frequency, which requires radical changes to the technologies currently used in LHCb. The hardware trigger is removed, and some of the detectors replaced. The VELO changes its tracking technology and silicon strips are replaced by 55 μm pitch silicon pixels. The readout chip for the VELO upgrade is the VeloPix ASIC. The number of readout channels increases to over 40 million, and the hottest ASIC is expected to produce the output data rate of 15 Gbit/s. New conditions challenge the software and the hardware side of the readout system and put special attention on the detector monitoring. This paper presents the upgraded VELO design and outlines the software aspects of the detector calibration in the upgrade I. An overview of the challenges foreseen for the upgrade II is given.

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