scholarly journals Ultra Wide Bandwidth Source Utilizing the Two Stream Instability

2021 ◽  
Author(s):  
Derek Neben
Keyword(s):  
Wide Bandwidth ◽  
Stream Instability

Design of a Source for GHz Ultra-Wide Bandwidth Applications Using the Two-Stream Instability

2020 ◽  
Author(s):  
Derek Neuen ◽  
Kip Bishofberger ◽  
Vitaly Pavlenko ◽  
Nikolai Yampolsky
Keyword(s):  
Wide Bandwidth ◽  
Stream Instability

THREE INTEGRATED GAINS OF WIDE BANDWIDTH MULTI-PUMPING RAMAN OPTICAL AMPLIFIER: THE MAXIMUM FLATNESS

2006 ◽  
Vol 16 (2) ◽  
pp. 1-14
Author(s):  
Moawad I. Moawad ◽  
Mahmoud M. A. Eid ◽  
Abd El-Naser A. Mohammed ◽  
Mahmoud M.A. Abd El-Whab
Keyword(s):  
Optical Amplifier ◽  
Wide Bandwidth

Ultra wide bandwidth v.a.d. fibre

1980 ◽  
Vol 16 (10) ◽  
pp. 391 ◽  
Author(s):  
M. Nakahara ◽  
S. Sudo ◽  
N. Inagaki ◽  
K. Yoshida ◽  
S. Shibuya ◽  
...  
Keyword(s):  
Wide Bandwidth

scholarly journals Fabrication and characterization of resistive double square loop arrays for ultra-wide bandwidth microwave absorption

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Ji-Young Jeong ◽  
Je-Ryung Lee ◽  
Hyeonjin Park ◽  
Joonkyo Jung ◽  
Doo-Sun Choi ◽  
...  
Keyword(s):  
Sheet Resistance ◽  
Manufacturing Process ◽  
End Milling ◽  
Milling Process ◽  
Wide Bandwidth ◽  
Machined Surface ◽  
Array Pattern ◽  
Micro End Milling ◽  
Array Structures ◽  
Printing Processes

AbstractMicrowave absorbers using conductive ink are generally fabricated by printing an array pattern on a substrate to generate electromagnetic fields. However, screen printing processes are difficult to vary the sheet resistance values for different regions of the pattern on the same layer, because the printing process deposits materials at the same height over the entire surface of substrate. In this study, a promising manufacturing process was suggested for engraved resistive double square loop arrays with ultra-wide bandwidth microwave. The developed manufacturing process consists of a micro-end-milling, inking, and planing processes. A 144-number of double square loop array was precisely machined on a polymethyl methacrylate workpiece with the micro-end-milling process. After engraving array structures, the machined surface was completely covered with the developed conductive carbon ink with a sheet resistance of 15 Ω/sq. It was cured at room temperature. Excluding the ink that filled the machined double square loop array, overflowed ink was removed with the planing process to achieve full filled and isolated resistive array patterns. The fabricated microwave absorber showed a small radar cross-section with reflectance less than − 10 dB in the frequency band range of 8.0–14.6 GHz.

scholarly journals Design and Analysis of Super Wideband Antenna for Microwave Applications

Sensors ◽  
2021 ◽  
Vol 21 (2) ◽  
pp. 477
Author(s):  
Warsha Balani ◽  
Mrinal Sarvagya ◽  
Ajit Samasgikar ◽  
Tanweer Ali ◽  
Pradeep Kumar
Keyword(s):  
Communication Systems ◽  
Equivalent Circuit Model ◽  
Wireless Communication Systems ◽  
Impedance Bandwidth ◽  
Frequency Range ◽  
Fractional Bandwidth ◽  
Wide Bandwidth ◽  
Wireless Applications ◽  
Frequency Constraint ◽  
Time Domain Characterization

In this article, a compact concentric structured monopole patch antenna for super wideband (SWB) application is proposed and investigated. The essential characteristics of the designed antenna are: (i) to attain super-wide bandwidth characteristics, the proposed antenna is emerged from a traditional circular monopole antenna and has obtained an impedance bandwidth of 38.9:1 (ii) another important characteristic of the presented antenna is its larger bandwidth dimension ratio (BDR) value of 6596 that is accomplished by augmenting the electrical length of the patch. The electrical dimension of the proposed antenna is 0.18λ×0.16λ (λ corresponds to the lower end operating frequency). The designed antenna achieves a frequency range from 1.22 to 47.5 GHz with a fractional bandwidth of 190% and exhibiting S11 < −10 dB in simulation. For validating the simulated outcomes, the antenna model is fabricated and measured. Good conformity is established between measured and simulated results. Measured frequency ranges from 1.25 to 40 GHz with a fractional bandwidth of 188%, BDR of 6523 and S11 < −10 dB. Even though the presented antenna operates properly over the frequency range from 1.22 to 47.5 GHz, the results of the experiment are measured till 40 GHz because of the high-frequency constraint of the existing Vector Network Analyzer (VNA). The designed SWB antenna has the benefit of good gain, concise dimension, and wide bandwidth above the formerly reported antenna structures. Simulated gain varies from 0.5 to 10.3 dBi and measured gain varies from 0.2 to 9.7 dBi. Frequency domain, as well as time-domain characterization, has been realized to guide the relevance of the proposed antenna in SWB wireless applications. Furthermore, an equivalent circuit model of the proposed antenna is developed, and the response of the circuit is obtained. The presented antenna can be employed in L, S, C, X, Ka, K, Ku, and Q band wireless communication systems.

scholarly journals Study on the Implementation of a Simple and Effective Memory System for an AI Chip

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1399
Author(s):  
Taepyeong Kim ◽  
Sangun Park ◽  
Yongbeom Cho
Keyword(s):  
High Speed ◽  
Memory Systems ◽  
Memory System ◽  
External Memory ◽  
Essential Factor ◽  
Wide Bandwidth ◽  
Reading And Writing ◽  
Data Skew ◽  
Lower Performance ◽  
Efficient Memory

In this study, a simple and effective memory system required for the implementation of an AI chip is proposed. To implement an AI chip, the use of internal or external memory is an essential factor, because the reading and writing of data in memory occurs a lot. Those memory systems that are currently used are large in design size and complex to implement in order to handle a high speed and a wide bandwidth. Therefore, depending on the AI application, there are cases where the circuit size of the memory system is larger than that of the AI core. In this study, SDRAM, which has a lower performance than the currently used memory system but does not have a problem in operating AI, was used and all circuits were implemented digitally for simple and efficient implementation. In particular, a delay controller was designed to reduce the error due to data skew inside the memory bus to ensure stability in reading and writing data. First of all, it verified the memory system based on the You Only Look Once (YOLO) algorithm in FPGA to confirm that the memory system proposed in AI works efficiently. Based on the proven memory system, we implemented a chip using Samsung Electronics’ 65 nm process and tested it. As a result, we designed a simple and efficient memory system for AI chip implementation and verified it with hardware.

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