Efficient Verification Using Design Commonalities

1997 ◽  
Author(s):  
Gitanjali Swamy
Keyword(s):  
Efficient Verification

scholarly journals Efficient Verification of Dicke States

2019 ◽  
Vol 12 (4) ◽  
Author(s):  
Ye-Chao Liu ◽  
Xiao-Dong Yu ◽  
Jiangwei Shang ◽  
Huangjun Zhu ◽  
Xiangdong Zhang
Keyword(s):  
Efficient Verification ◽  
Dicke States

scholarly journals Towards efficient verification of population protocols

2021 ◽  
Author(s):  
Michael Blondin ◽  
Javier Esparza ◽  
Stefan Jaax ◽  
Philipp J. Meyer
Keyword(s):  
Linear Constraints ◽  
Computational Power ◽  
High Complexity ◽  
Reachability Problem ◽  
Population Protocols ◽  
Finite State ◽  
State Agents ◽  
Efficient Verification ◽  
Primitive Recursive ◽  
Very High

AbstractPopulation protocols are a well established model of computation by anonymous, identical finite-state agents. A protocol is well-specified if from every initial configuration, all fair executions of the protocol reach a common consensus. The central verification question for population protocols is the well-specification problem: deciding if a given protocol is well-specified. Esparza et al. have recently shown that this problem is decidable, but with very high complexity: it is at least as hard as the Petri net reachability problem, which is -hard, and for which only algorithms of non-primitive recursive complexity are currently known. In this paper we introduce the class $${ WS}^3$$ WS 3 of well-specified strongly-silent protocols and we prove that it is suitable for automatic verification. More precisely, we show that $${ WS}^3$$ WS 3 has the same computational power as general well-specified protocols, and captures standard protocols from the literature. Moreover, we show that the membership and correctness problems for $${ WS}^3$$ WS 3 reduce to solving boolean combinations of linear constraints over $${\mathbb {N}}$$ N . This allowed us to develop the first software able to automatically prove correctness for all of the infinitely many possible inputs.

scholarly journals A Unique Test Bench for Various System-on-a-Chip

2017 ◽  
Vol 7 (6) ◽  
pp. 3318 ◽  
Author(s):  
Sridevi Chitti ◽  
P. Chandrasekhar ◽  
M. Asharani
Keyword(s):  
Intellectual Property ◽  
Test Bench ◽  
General Purpose ◽  
Technology Tools ◽  
Automated Test ◽  
System On A Chip ◽  
Verification Process ◽  
Verification Methodology ◽  
Efficient Verification ◽  
State Of Art

This paper discusses a standard flow on how an automated test bench environment which is randomized with constraints can verify a SOC efficiently for its functionality and coverage. Today, in the time of multimillion gate ASICs, reusable intellectual property (IP), and system-on-a-chip (SoC) designs, verification consumes about 70 % of the design effort. Automation means a machine completes a task autonomously, quicker and with predictable results. Automation requires standard processes with well-defined inputs and outputs. By using this efficient methodology it is possible to provide a general purpose automation solution for verification, given today’s technology. Tools automating various portions of the verification process are being introduced. Here, we have Communication based SOC The content of the paper discusses about the methodology used to verify such a SOC-based environment. Cadence Efficient Verification Methodology libraries are explored for the solution of this problem. We can take this as a state of art approach in verifying SOC environments. The goal of this paper is to emphasize the unique testbench for different SOC using Efficient Verification Constructs implemented in system verilog for SOC verification.

scholarly journals Efficient Verification of Sequential and Concurrent C Programs

2004 ◽  
Vol 25 (2/3) ◽  
pp. 129-166 ◽  
Author(s):  
S. Chaki ◽  
E. Clarke ◽  
A. Groce ◽  
J. Ouaknine ◽  
O. Strichman ◽  
...  
Keyword(s):  
C Programs ◽  
Efficient Verification
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