Low Leakage Sequential MTCMOS Shift Register for Mitigation of Ground Fluctuations Noise During Complete Reactivation Process

2018 ◽  
Author(s):  
Anjan Kumar ◽  
Devendra Chack ◽  
Manisha Pattanaik
Keyword(s):  
Shift Register ◽  
Low Leakage ◽  
Reactivation Process

Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures

2011 ◽  
Vol E94-A (12) ◽  
pp. 2669-2675 ◽  
Author(s):  
Chikara HAMANAKA ◽  
Ryosuke YAMAMOTO ◽  
Jun FURUTA ◽  
Kanto KUBOTA ◽  
Kazutoshi KOBAYASHI ◽  
...  
Keyword(s):  
Shift Register ◽  
Flip Flop ◽  
Variation Tolerance ◽  
Modular Redundancy

Integrated ESD Robustness through Device Analysis of Ultra-Small Low Voltage Power MOSFETs

2014 ◽  
Author(s):  
Ian Kearney ◽  
Hank Sung
Keyword(s):  
New Product Development ◽  
Silicon Oxide ◽  
Low Voltage ◽  
Photon Emission ◽  
Electrical Characterization ◽  
Power Mosfets ◽  
Low Leakage ◽  
A Cell ◽  
Thermographic Analysis ◽  
Voltage Spike

Abstract Low voltage power MOSFETs often integrate voltage spike protection and gate oxide ESD protection. The basic concept of complete-static protection for the power MOSFETs is the prevention of static build-up where possible and the quick, reliable removal of existing charges. The power MOSFET gate is equivalent to a low voltage low leakage capacitor. The capacitor plates are formed primarily by the silicon gate and source metallization. The capacitor dielectric is the silicon oxide gate insulation. Smaller devices have less capacitance and require less charge per volt and are therefore more susceptible to ESD than larger MOSFETs. A FemtoFETTM is an ultra-small, low on-resistance MOSFET transistor for space-constrained handheld applications, such as smartphones and tablets. An ESD event, for example, between a fingertip and the communication-port connectors of a cell phone or tablet may cause permanent system damage. Through electrical characterization and global isolation by active photon emission, the authors identify and distinguish ESD failures. Thermographic analysis provided additional insight enabling further separation of ESD failmodes. This paper emphasizes the role of failure analysis in new product development from the create phase through to product ramp. Coupled with device electrical simulation, the analysis observations led to further design enhancement.

Design of feedback shift register based on chaos

2009 ◽  
Vol 28 (10) ◽  
pp. 2704-2706 ◽  
Author(s):  
Chao MA ◽  
Yu-zhen LU
Keyword(s):  
Shift Register ◽  
Feedback Shift Register

Optimization of sol-gel based fibre-optic cholinesterase biosensor for the determination of organophosphorus pesticides

2000 ◽  
Vol 42 (7-8) ◽  
pp. 283-290 ◽  
Author(s):  
H.-C. Tsai ◽  
R.-A. Doong
Keyword(s):  
Fiber Optic ◽  
Ph Value ◽  
Rapid Determination ◽  
Organophosphorus Pesticides ◽  
Sol Gel ◽  
Neutral Red ◽  
Fluorescent Indicators ◽  
Low Leakage ◽  
Fiber Optic System

A sol-gel based fiber-optic biosensor with acetylcholinesterase as the biorecognition element has been developed for the rapid determination of organophosphorus pesticides. Nine fluorescent indicators, acridine, acridine orange, neutral red, DAPI, rhodamine B, fluorescein, umbelliferone, FITC on celite and FITC-dextran, have been examined to optimize the fiber-optic system. Results showed that acridine and FITCs were sensitive to the change of pH value caused by the enzyme-substrate catalysis reaction. However, the sensitivity of acridine was 260 times lower than that of FITCs. Higher toxicity of acridine to acetylcholinesterase than FITC was also observed. Moreover, the high-molecular-weight FITC-dextran showed low leakage rate when immobilizing using sol-gel technology, showing that the FITC-dextran was a suitable pH sensitive fluorescent indicator for the OPPs biosensor. The response of the fiber-optic biosensor to the substrate, acetylcholine, was highly reproducible (RSD=3.5%). A good linearity of acetylcholine in the range from 0.5 to 20 mM was also obtained (R2=0.98). Furthermore, a 30% inhibition can be achieved in 30min when 152 ppb paraoxon was added into the system. The results show the possibility for real-time determination of organophosphorus pesticides by using the biosensor developed in this study.

Design and Implementation of an Efficient Parallel LFSR Architecture for Wireless Communication Systems

2019 ◽  
Vol 14 ◽  
Author(s):  
A. Suresh Babu ◽  
B. Anand
Keyword(s):  
Wireless Communication ◽  
Power Consumption ◽  
Low Power ◽  
Communication Systems ◽  
High Speed ◽  
Design Tool ◽  
Shift Register ◽  
Linear Feedback ◽  
Wireless Communication Systems ◽  
Coverage Area

: A Linear Feedback Shift Register (LFSR) considers a linear function typically an XOR operation of the previous state as an input to the current state. This paper describes in detail the recent Wireless Communication Systems (WCS) and techniques related to LFSR. Cryptographic methods and reconfigurable computing are two different applications used in the proposed shift register with improved speed and decreased power consumption. Comparing with the existing individual applications, the proposed shift register obtained >15 to <=45% of decreased power consumption with 30% of reduced coverage area. Hence this proposed low power high speed LFSR design suits for various low power high speed applications, for example wireless communication. The entire design architecture is simulated and verified in VHDL language. To synthesis a standard cell library of 0.7um CMOS is used. A custom design tool has been developed for measuring the power. From the results, it is obtained that the cryptographic efficiency is improved regarding time and complexity comparing with the existing algorithms. Hence, the proposed LFSR architecture can be used for any wireless applications due to parallel processing, multiple access and cryptographic methods.

High nonlinearity and low leakage current SnO2 varistor ceramics by co-doping with yttrium and tantalum

2021 ◽  
Vol 285 ◽  
pp. 129120
Author(s):  
Wenxin Liang ◽  
Hongfeng Zhao ◽  
Xiaoji Meng ◽  
Shaohua Fan ◽  
Qingyun Xie
Keyword(s):  
Leakage Current ◽  
Co Doping ◽  
High Nonlinearity ◽  
Low Leakage ◽  
Low Leakage Current

scholarly journals A Novel Cross-Latch Shift Register Scheme for Low Power Applications

2020 ◽  
Vol 11 (1) ◽  
pp. 129
Author(s):  
Po-Yu Kuo ◽  
Ming-Hwa Sheu ◽  
Chang-Ming Tsai ◽  
Ming-Yan Tsai ◽  
Jin-Fa Lin
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Electrical Power ◽  
Average Power ◽  
Leakage Power ◽  
Shift Register ◽  
Cmos Process ◽  
Average Power Consumption ◽  
Simulation Results ◽  
Layout Area

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

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