Reliability-Driven CAD System for Deep-Submicron VLSI Circuits

1998 ◽  
Author(s):  
S. M. Kang ◽  
E. Rosenbaum ◽  
Y. K. Cheng ◽  
L. P. Yuan ◽  
T. Li
Keyword(s):  
Deep Submicron ◽  
Vlsi Circuits ◽  
Cad System

scholarly journals An Efficient Power Optimized 32 bit BCD Adder Using Multi-Channel Technique

2017 ◽  
Vol 6 (02) ◽  
pp. 07-12
Author(s):  
Diksha Siddhamshittiwar
Keyword(s):  
Average Power ◽  
Full Adder ◽  
Deep Submicron ◽  
Power Reduction ◽  
Vlsi Circuits ◽  
Power Gating ◽  
Static Power ◽  
Simulation Results ◽  
Efficient Power ◽  
Standby Mode

Static power reduction is a challenge in deep submicron VLSI circuits. In this paper 28T full adder circuit, 14T full adder circuit and 32 bit power gated BCD adder using the full adders respectively were designed and their average power was compared. In existing work a conventional full adder is designed using 28T and the same is used to design 32 bit BCD adder. In the proposed architecture 14T transmission gate based power gated full adder is used for the design of 32 bit BCD adder. The leakage supremacy dissipated during standby mode in all deep submicron CMOS devices is reduced using efficient power gating and multi-channel technique. Simulation results were obtained using Tanner EDA and TSMC_180nm library file is used for the design of 28T full adder, 14T full adder and power gated BCD adder and a significant power reduction is achieved in the proposed architecture.

Adaptive Thermal Monitoring of Deep-Submicron CMOS VLSI Circuits

2013 ◽  
Vol 9 (4) ◽  
pp. 403-413
Author(s):  
Amir Zjajo ◽  
Nick van der Meijs ◽  
Rene van Leuken
Keyword(s):  
Deep Submicron ◽  
Vlsi Circuits ◽  
Thermal Monitoring ◽  
Submicron Cmos ◽  
Cmos Vlsi

scholarly journals Fabrication Process and Properties of Fully-Planarized Deep-Submicron Nb/Al– $\hbox{AlO}_{\rm x}\hbox{/Nb} $ Josephson Junctions for VLSI Circuits

2015 ◽  
Vol 25 (3) ◽  
pp. 1-12 ◽  
Author(s):  
Sergey K. Tolpygo ◽  
Vladimir Bolkhovsky ◽  
Terence J. Weir ◽  
Leonard M. Johnson ◽  
Mark A. Gouker ◽  
...  
Keyword(s):  
Josephson Junctions ◽  
Deep Submicron ◽  
Vlsi Circuits ◽  
Fabrication Process

scholarly journals Analysis of Clock trees for optimization through Multi point Clock Tree Synthesis

2020 ◽  
Vol 8 (5) ◽  
pp. 1879-1882
Keyword(s):  
Rapid Development ◽  
Synthesis Method ◽  
Deep Submicron ◽  
Vlsi Circuits ◽  
Clock Skew ◽  
Clock Tree ◽  
Timing Closure ◽  
Clock Tree Synthesis ◽  
Tree Synthesis ◽  
The Given

With rapid development of deep submicron (DSM) VLSI circuits design, building clock tree with minimal insertion delays and minimal skews has turned out to be challenging. In this Paper for a given specified block with a latency of 530 ns it is aimed to achieve a latency of 400ns and achieve optimal power. Here a Clock Tree Synthesis method is used to reduce the latency and obtain the timing closure for the given block. The analysis is made and compared in terms of clock skew and insertion delay by varying the tap points. In this process of achieving the timing closure it is observed power has optimized by selecting the appropriate tap points.

TECHNIQUES FOR LOW LEAKAGE NANOSCALE VLSI CIRCUITS: A COMPARATIVE STUDY

2014 ◽  
Vol 23 (05) ◽  
pp. 1450061 ◽  
Author(s):  
VIJAY KUMAR SHARMA ◽  
MANISHA PATTANAIK
Keyword(s):  
Threshold Voltage ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Deep Submicron ◽  
Leakage Power ◽  
Vlsi Circuits ◽  
Oxide Semiconductor ◽  
Leakage Reduction ◽  
Reduction Techniques ◽  
Leakage Power Dissipation

Since the last two decades, the trend of device miniaturization has increased to get better performance with a smaller area of the logic functions. In deep submicron regime, the demand of fabrication of nanoscale Complementary metal oxide semiconductor (CMOS) VLSI circuits has increased due to evaluation of modern successful portable systems. Leakage power dissipation and reliability issues are major concerns in deep submicron regime for VLSI chip designers. Power supply voltage has been scaled down to maintain the performance yield in future deep submicron regime. The threshold voltage is the critical parameter to trade-off the performance yield and leakage power dissipation in nanoscaled devices. Low threshold voltage improves the device characteristics with large leakage power in nanoscaled devices. Several leakage reduction techniques at different levels are used to mitigate the leakage power dissipation. Lower leakage power increases the reliability by reducing the cooling cost of the portable systems. In this article, we are presenting the explanatory general review of the commonly used leakage reduction techniques at circuit level. We have analyzed the NAND3 gate using HSPICE EDA tool for leakage power dissipation at different technology nodes in active as well as standby modes. Process, voltage and temperature effects are checked for reliability purpose. Our comparative results and discussion of different leakage reduction techniques are very useful to illustrate the effective technique in active and standby modes.

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