Memory Contention in Scalable Cache-Coherent Multiprocessors

1993 ◽  
Author(s):  
Ricardo Bianchini ◽  
Mark E. Crovella ◽  
Leonidas Kontothanassiss ◽  
Thomas J. LeBlanc
Keyword(s):  
Memory Contention

scholarly journals Scheduling support for transactional memory contention management

2010 ◽  
Vol 45 (5) ◽  
pp. 79-90 ◽  
Author(s):  
Walther Maldonado ◽  
Patrick Marlier ◽  
Pascal Felber ◽  
Adi Suissa ◽  
Danny Hendler ◽  
...  
Keyword(s):  
Transactional Memory ◽  
Contention Management ◽  
Memory Contention

scholarly journals Performance of MC2 and the ECMWF IFS Forecast Model on the Fujitsu VPP700 and NEC SX-4M

2000 ◽  
Vol 8 (1) ◽  
pp. 23-30 ◽  
Author(s):  
Michel Desgagné ◽  
Stephen Thomas ◽  
Michel Valin
Keyword(s):  
Message Passing ◽  
Forecast Model ◽  
Cmos Technology ◽  
Single Node ◽  
Fibre Channel ◽  
Low Power Cmos ◽  
Memory Contention ◽  
Execution Rates ◽  
Vector Processors ◽  
Crossbar Network

The NEC SX-4M cluster and Fujitsu VPP700 supercomputers are both based on custom vector processors using low-power CMOS technology. Their basic architectures and programming models are however somewhat different. A multi-node SX-4M cluster contains up to 32 processors per shared memory node, with a maximum of 16 nodes connected via the proprietary NEC IXS fibre channel crossbar network. A hybrid combination of inter-node MPI message-passing with intra-node tasking or threads is possible. The Fujitsu VPP700 is a fully distributed-memory vector machine with a crossbar interconnect which also supports MPI. The parallel performance of the MC2 model for high-resolution mesoscale forecasting over large domains and of the IFS RAPS 4.0 benchmark are presented for several different machine configurations. These include an SX-4/32, an SX-4/32M cluster and up to 100 PE's of the VPP700. Our results indicate that performance degradation for both models on a single SX-4 node is primarily due to memory contention within the internal crossbar switch. Multinode SX-4 performance is slightly better than single node. Longer vector lengths and SDRAM memory on the VPP700 result in lower per processor execution rates. Both models achieve close to ideal scaling on the VPP700.

A framework for memory contention analysis in multi-core platforms

2015 ◽  
Vol 52 (3) ◽  
pp. 272-322 ◽  
Author(s):  
Dakshina Dasari ◽  
Vincent Nelis ◽  
Benny Akesson
Keyword(s):  
Memory Contention

scholarly journals Unraveling Network-Induced Memory Contention: Deeper Insights with Machine Learning

2018 ◽  
Vol 29 (8) ◽  
pp. 1907-1922
Author(s):  
Taylor Liles Groves ◽  
Ryan E. Grant ◽  
Aaron Gonzales ◽  
Dorian Arnold
Keyword(s):  
Machine Learning ◽  
Memory Contention

scholarly journals Profiling and controlling I/O‐related memory contention in COTS heterogeneous platforms

2021 ◽  
Author(s):  
Matteo Zini ◽  
Giorgiomaria Cicero ◽  
Daniel Casini ◽  
Alessandro Biondi
Keyword(s):  
Heterogeneous Platforms ◽  
Memory Contention
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