A New Vertical Interference Test Method in a Three Layer Reservoir With an Unstable Impermeable Interlayer

1996 ◽  
Author(s):  
Tang Xijian ◽  
Liu Shaowu ◽  
Wang Yanfeng
Keyword(s):  
Test Method ◽  
Interference Test ◽  
Vertical Interference Test

Design of Vehicle CAN-Network Bit-Level Interference Testing System Based on FPGA

2013 ◽  
Vol 765-767 ◽  
pp. 129-133
Author(s):  
An Yu Cheng ◽  
Ju Lin Zhang ◽  
Gang Wang
Keyword(s):  
Fault Tolerance ◽  
Test Method ◽  
Testing System ◽  
System Behavior ◽  
Verilog Hdl ◽  
Data Link ◽  
Link Layer ◽  
Data Link Layer ◽  
Interference Test ◽  
Bit Stream

In order to ensure the system behavior of vehicle CAN network and its ECU nodes meet the requirements of high fault tolerance in complex communication conditions. The CAN networks bit-level interference test method in data link layer based on FPGA was studied. Monitored bit stream and embedded interference by behavior level description through Verilog HDL based on FPGA. Simultaneously, host computer configuration interface which is based on Visual C++ was developed. Using the design of this paper interfered the CAN network evidenced the design can implement interference effectively and flexibly to CAN, reliable stability and high fault tolerance of CAN network can be verified.

Utilizing Advanced Logs for Flow Unit Classification in Vertical Interference Test Modeling

2019 ◽  
Author(s):  
Arvind Kumar ◽  
Arjit Gidwani ◽  
Suraj Singh ◽  
Tety Wydiabhakti ◽  
Siddhartha Mishra
Keyword(s):  
Flow Unit ◽  
Interference Test ◽  
Vertical Interference Test
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