The Future of Industrial High Performance Paper

2013 ◽  
Vol 69 (3) ◽  
pp. P_91-P_93
Author(s):  
YOSHITSUGU HAMA
Keyword(s):  
High Performance ◽  
The Future

scholarly journals PIC methods in astrophysics: simulations of relativistic jets and kinetic physics in astrophysical systems

2021 ◽  
Vol 7 (1) ◽  
Author(s):  
Kenichi Nishikawa ◽  
Ioana Duţan ◽  
Christoph Köhn ◽  
Yosuke Mizuno
Keyword(s):  
Plasma Physics ◽  
Magnetic Reconnection ◽  
Laser Plasma ◽  
High Performance ◽  
Relativistic Jets ◽  
Astrophysical Plasmas ◽  
Computing Power ◽  
Particle In Cell ◽  
The Future ◽  
Pic Method

AbstractThe Particle-In-Cell (PIC) method has been developed by Oscar Buneman, Charles Birdsall, Roger W. Hockney, and John Dawson in the 1950s and, with the advances of computing power, has been further developed for several fields such as astrophysical, magnetospheric as well as solar plasmas and recently also for atmospheric and laser-plasma physics. Currently more than 15 semi-public PIC codes are available which we discuss in this review. Its applications have grown extensively with increasing computing power available on high performance computing facilities around the world. These systems allow the study of various topics of astrophysical plasmas, such as magnetic reconnection, pulsars and black hole magnetosphere, non-relativistic and relativistic shocks, relativistic jets, and laser-plasma physics. We review a plethora of astrophysical phenomena such as relativistic jets, instabilities, magnetic reconnection, pulsars, as well as PIC simulations of laser-plasma physics (until 2021) emphasizing the physics involved in the simulations. Finally, we give an outlook of the future simulations of jets associated to neutron stars, black holes and their merging and discuss the future of PIC simulations in the light of petascale and exascale computing.

Hierarchical porous CeO2 micro rice supported Ni foam binder free electrode and its enhanced pseudocapacitor performance by redox additive electrolyte

2021 ◽  
Author(s):  
Arunpandiyan Surulinathan ◽  
Raja Annamalai ◽  
Vinoth S ◽  
Alagarsamy Pandikumar ◽  
Ayyaswamy Arivarasan
Keyword(s):  
High Performance ◽  
Ni Foam ◽  
Hierarchically Porous ◽  
Hierarchical Porous ◽  
The Future ◽  
Binder Free ◽  
Supported Ni

Developing high-performance, robust, and economic supercapacitor is a promising path to the future electric vehicle’s technology. Herein, a hierarchically porous CeO2 micro rice was attached on the Ni foam surface...

scholarly journals Homogeneous Catalyzed Valorization of Furanics: A Sustainable Bridge to Fuels and Chemicals

Catalysts ◽  
2021 ◽  
Vol 11 (11) ◽  
pp. 1371
Author(s):  
Rosa Padilla ◽  
Sakhitha Koranchalil ◽  
Martin Nielsen
Keyword(s):  
Homogeneous Catalysis ◽  
High Performance ◽  
Sustainable Production ◽  
Biomass Valorization ◽  
Complex Chemical ◽  
Mild Conditions ◽  
High Performance Polymers ◽  
Organometallic Catalysis ◽  
The Future ◽  
Fuels And Chemicals

The development of efficient biomass valorization is imperative for the future sustainable production of chemicals and fuels. Particularly, the last decade has witnessed the development of a plethora of effective and selective transformations of bio-based furanics using homogeneous organometallic catalysis under mild conditions. In this review, we describe some of the advances regarding the conversion of target furanics into value chemicals, monomers for high-performance polymers and materials, and pharmaceutical key intermediates using homogeneous catalysis. Finally, the incorporation of furanic skeletons into complex chemical architectures by multifunctionalization routes is also described.

Cost Breakdown of 2.5D and 3D Packaging

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 000324-000341 ◽  
Author(s):  
Chet Palesko ◽  
Amy Palesko
Keyword(s):  
High Performance ◽  
Cost Model ◽  
High Price ◽  
Future Cost ◽  
The Future ◽  
3D Packaging ◽  
Long Time ◽  
Design Characteristics ◽  
And Performance ◽  
The Cost

2.5D and 3D packaging can provide significant size and performance advantages over other packaging technologies. However, these advantages usually come at a high price. Since 2.5D and 3D packaging costs are significant, today they are only used if no other option can meet the product requirements, and most of these applications are relatively low volume. Products such as high end FPGAs, high performance GPUs, and high bandwidth memory are great applications but none have volume requirements close to mobile phones or tablets. Without the benefit of volume production, the cost of 2.5D and 3D packaging could stay high for a long time. In this paper, we will provide cost model results of a complete 2.5D and 3D manufacturing process. Each manufacturing activity will be included and the key cost drivers will be analyzed regarding future cost reductions. Expensive activities that are well down the learning curve (RDL creation, CMP, etc.) will probably not change much in the future. However, expensive activities that are new to this process (DRIE, temporary bond/debond, etc.) provide good opportunities for cost reduction. A variety of scenarios will be included to understand how design characteristics impact the cost. Understanding how and why the dominant cost components will change over time is critical to accurately predicting the future cost of 2.5D and 3D packaging.

CMOS DEVICES ARCHITECTURES AND TECHNOLOGY INNOVATIONS FOR THE NANOELECTRONICS ERA

2006 ◽  
Vol 16 (01) ◽  
pp. 193-219 ◽  
Author(s):  
S. DELEONIBUS ◽  
B. de SALVO ◽  
T. ERNST ◽  
O. FAYNOT ◽  
T. POIROUX ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Gate Dielectric ◽  
Low Voltage ◽  
Short Channel Effects ◽  
Short Channel ◽  
Trade Offs ◽  
Future System ◽  
The Future ◽  
Channel Effects

Innovations in electronics history have been possible because of the strong association of devices and materials research. The demand for low voltage, low power and high performance are the great challenges for engineering of sub 50nm gate length CMOS devices. Functional CMOS devices in the range of 5 nm channel length have been demonstrated. The alternative architectures allowing to increase devices drivability and reduce power are reviewed through the issues to address in gate/channel and substrate, gate dielectric as well as source and drain engineering. HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. It will be very difficult to compete with CMOS logic because of the low series resistance required to obtain high performance. By introducing new materials ( Ge , diamond/graphite Carbon, HiK, …), Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating new disruptive devices. The association of C-diamond with HiK as a combination for new functionalized Buried Insulators, for example, will bring new ways of improving short channel effects and suppress self-heating. That will allow new optimization of Ion-Ioff trade offs. The control of low power dissipation and short channel effects together with high performance will be the major challenges in the future.

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