scholarly journals HPX - The C++ Standard Library for Parallelism and Concurrency

2020 ◽  
Vol 5 (53) ◽  
pp. 2352 ◽  
Author(s):  
Hartmut Kaiser ◽  
Patrick Diehl ◽  
Adrian Lemoine ◽  
Bryce Lelbach ◽  
Parsa Amini ◽  
...  
Keyword(s):  
Parallelism And Concurrency ◽  
Standard Library

scholarly journals An asynchronous and task-based implementation of peridynamics utilizing HPX—the C++ standard library for parallelism and concurrency

2020 ◽  
Vol 2 (12) ◽  
Author(s):  
Patrick Diehl ◽  
Prashant K. Jha ◽  
Hartmut Kaiser ◽  
Robert Lipton ◽  
Martin Lévesque
Keyword(s):  
Parallelism And Concurrency ◽  
Standard Library ◽  
And Task

Encapsulation and the C++ class

2018 ◽  
Author(s):  
Joseph F. Boudreau ◽  
Eric S. Swanson
Keyword(s):  
Program Design ◽  
Internal Representation ◽  
Floating Point ◽  
Complex Class ◽  
Numerical Examples ◽  
Important Notion ◽  
Standard Library

Built-in datatypes and C++ classes are introduced in this chapter, and discussed in relation to the important notion of encapsulation, which refers to the separation between the internal representation of the datatype and the operations to which it responds. Encapsulation later becomes an important consideration in the design of custom C++ classes that programmers develop themselves. It is illustrated with built-in floating-point datatypes float and double and with the complex class from the C++ standard library. While a sophisticated programmer is aware of the internal representation of data and its resulting limitations, encapsulation allows one to consider these as details and frees one to think at a higher level of program design. Some simple numerical examples are discussed in the text and in the exercises.

C++17 Standard Library Quick Reference

2019 ◽  
Author(s):  
Peter Van Weert ◽  
Marc Gregoire
Keyword(s):  
Standard Library

The Standard Library

Elements of C ◽  
1986 ◽  
pp. 159-196
Author(s):  
Morton H. Lewin
Keyword(s):  
Standard Library

scholarly journals High-level multicore programming with C++11

2012 ◽  
Vol 9 (3) ◽  
pp. 1187-1202
Author(s):  
Zalán Szűgyi ◽  
Márk Török ◽  
Norbert Pataki ◽  
Tamás Kozsik
Keyword(s):  
Programming Languages ◽  
Multicore Processors ◽  
Multicore Programming ◽  
C Programming Language ◽  
C Programming ◽  
Template Library ◽  
Standard Template ◽  
High Level ◽  
Standard Template Library ◽  
Standard Library

Nowadays, one of the most important challenges in programming is the efficient usage of multicore processors. All modern programming languages support multicore programming at native or library level. C++11, the next standard of the C++ programming language, also supports multithreading at a low level. In this paper we argue for some extensions of the C++ Standard Template Library based on the features of C++11. These extensions enhance the standard library to be more powerful in the multicore realm. Our approach is based on functors and lambda expressions, which are major extensions in the language. We contribute three case studies: how to efficiently compose functors in pipelines, how to evaluate boolean operators in parallel, and how to efficiently accumulate over associative functors.

scholarly journals Sense Amplifier Half Buffer Based Ripple Carry Adder for IEEE 754 Standards

2020 ◽  
Vol 9 (3) ◽  
pp. 854-858
Keyword(s):  
Power Dissipation ◽  
Logic Design ◽  
Sense Amplifier ◽  
Ripple Carry Adder ◽  
Null Convention Logic ◽  
Systems And Control ◽  
Prime Objective ◽  
Minimum Delay ◽  
And Control ◽  
Standard Library

Addition is a specifically used indispensable computation used for most of the applications including digital systems and control systems. Adder is a primitive constituent used in the construction of digital IC; also it is an essential part of signal processing applications like DSP. The speed of an adder circuit holds a considerable influence on the total performance of digital circuits. The prime objective of this research is to design ripple carry adder using different asynchronous logics like Multithreshold null convention logic (MTNCL), Multi-threshold dual spacer dual rail delay insensitive logic (MTD3L) and proposed Sense amplifier half buffer logic (SAHB). SAHB is an asynchronous Quasi-Delay -Insensitive (QDI) method used to achieve significant functional speed of the circuit. The standard library cells (2-input AND/NAND, 2-input OR/NOR, 2-input XOR/XNOR) are designed using proposed SAHB logic to design an 8- bit Ripple Carry Adder circuit. The proposed SAHB logic design provides the solution of minimum delay with improved speed compared to the existing logic design techniques. The asynchronous logics are designed using mentor graphics tool with 130nm technology. Various performances attributes like power dissipation, delay and energy are tabulated and compared with existing logics

Using Standard Library Packages

Go Recipes ◽  
2016 ◽  
pp. 103-127
Author(s):  
Shiju Varghese
Keyword(s):  
Standard Library
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