scholarly journals Development of a Portable Multipurpose Controller for Mechatronics Education

2007 ◽  
Vol 19 (2) ◽  
pp. 223-231 ◽  
Author(s):  
Kazuhito Hyodo ◽  
◽  
Hirokazu Noborisaka ◽  
Keijiro Yamamoto ◽  
Takashi Yada ◽  
...  
Keyword(s):  
User Interface ◽  
Field Programmable Gate Array ◽  
System On Chip ◽  
Computational Power ◽  
Educational Materials ◽  
Control Module ◽  
Field Programmable ◽  
On Chip ◽  
Interactive User ◽  
Interactive User Interface

The control module we developed for mechatronics education, consists of a Field-programmable gate array (FPGA), a Programmable System-On-Chip (PSoC) and Game Boy Advance (GBA). The FPGA and PSoC provide a reconfigurable peripheral module and the GBA provides computational power and an interactive user interface. The interactive user interface is very useful for developing educational materials, and the control module enables educators to develop a variety of educational materials.

scholarly journals A Hardware Accelerator for the Inference of a Convolutional Neural network

2019 ◽  
Vol 30 (1) ◽  
pp. 107-116 ◽  
Author(s):  
Edwin González ◽  
Walter D. Villamizar Luna ◽  
Carlos Augusto Fajardo Ariza
Keyword(s):  
Field Programmable Gate Array ◽  
System On Chip ◽  
Software Implementation ◽  
Hardware Accelerator ◽  
Processing Scheme ◽  
Field Programmable ◽  
Computationally Intensive ◽  
On Chip ◽  
Memory Resources ◽  
Better Than

Convolutional Neural Networks (CNNs) are becoming increasingly popular in deep learning applications, e.g. image classification, speech recognition, medicine, to name a few. However, the CNN inference is computationally intensive and demanding a large among of memory resources. In this work is proposed a CNN inference hardware accelerator, which was implemented in a co-processing scheme. The aim is to reduce the hardware resources and achieve the better possible throughput. The design was implemented in the Digilent Arty Z7-20 development board, which is based on System on Chip (SoC) Zynq-7000 of Xilinx. Our implementation achieved a  of accuracy for the MNIST database using only 12-bits fixed-point format. The results show that the co-processing scheme operating at a conservative speed of 100 MHz can identify around 441 images per second, which is about 17% times faster than a 650 MHz - software implementation. It is difficult to compare our results against other implementations based on Field-Programmable Gate Array (FPGA), because the others implementations are not exactly like ours. However, some comparisons, regarding the logical resources used and accuracy, suggest that our work could be better than previous works.

scholarly journals Remote TSN Frame Encapsulation by means of FPGA

2021 ◽  
Author(s):  
Jaime Jiménez ◽  
Igor Rodríguez ◽  
David Reguilón ◽  
Aitzol Zuloaga ◽  
Jesús Lázaro
Keyword(s):  
Real Time ◽  
Field Programmable Gate Array ◽  
Industry 4.0 ◽  
Frame Analysis ◽  
System On Chip ◽  
The Other ◽  
Ideal Solution ◽  
Field Programmable ◽  
Real Time Transmission ◽  
On Chip

Abstract TSN (Time-Sensitive Networking) has replaced outdated Fieldbus and non-deterministic Ethernet in the Industry 4.0. Field buses are not capable of providing neither connection for industry 4.0 IoT (Internet of Things) nor compatibility between different manufacturers. On the other hand, Ethernet is not able to ensure real-time. On the contrary, TSN guarantees real-time transmission, IoT and compatibility between devices. However, adapting to frequently changing needs makes TSN protocol evolve continuously. For this reason, devices for TSN analysis, such as PCs or not advanced frame analysis equipment are not able to process TSN packets at the speed that standard advances, discarding them as wrong frames. The integration of a System on Chip (SoC) that contains an FPGA (Field Programmable Gate Array) and a microcontroller, with capacity for reconfiguration and monitoring of the frames in the protocol, would be an ideal solution to this problem. This paper describes how to encapsulate TSN frames in Ethernet packets using an FPGA. Such Ethernet frames can subsequently be decapsulated, i.e. in a PC, and thus enable analysing TSN traffic in nonspecialized devices.

Implementing the open master hearing aid on a system-on-chip field programmable gate array

2020 ◽  
Vol 148 (4) ◽  
pp. 2508-2508
Author(s):  
Ross Snider ◽  
Matthew Blunt ◽  
Trevor Vannoy ◽  
Dustin Sobrero ◽  
Dylan Wickham ◽  
...  
Keyword(s):  
Field Programmable Gate Array ◽  
Hearing Aid ◽  
System On Chip ◽  
Field Programmable ◽  
Gate Array ◽  
On Chip
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