An Efficient Specification for System Verification
2006 ◽
Vol 10
(6)
◽
pp. 931-938
Keyword(s):
In design of complex and large scale systems, system verification has played an important role. In this article, we focus on specification process of model checking in system verifications. Modeled systems are in general specified by temporal formulas of computation tree logic, and users must know well about temporal specification because the specification might be complex. We propose a method by which specifications with temporal formulas are obtained inductively. We will show verification results using the proposed temporal formula specification method, and show that amount of memory, OBDD nodes, and execution time are reduced.
2005 ◽
Vol 9
(3)
◽
pp. 321-328
2012 ◽
Vol 23
(7)
◽
pp. 1656-1668
◽
2010 ◽
Vol 1
(2)
◽
pp. 64-90
◽