41.3: 5° SiOx Deposition Alignment: A Possible Solution for the Low Power LCDs Using Low-Frequency Applied Voltage Waveforms

2010 ◽  
Vol 41 (1) ◽  
pp. 587
Author(s):  
Yi Huang ◽  
Philip J. Bos ◽  
Achintya Bhowmik
Keyword(s):  
Low Power ◽  
Applied Voltage ◽  
Low Frequency

Design Optimization of Low Power and Low Frequency Vibration Based MEMS Energy Harvester

2013 ◽  
Vol 475-476 ◽  
pp. 1624-1628
Author(s):  
Hasnizah Aris ◽  
David Fitrio ◽  
Jack Singh
Keyword(s):  
Low Power ◽  
Energy Harvester ◽  
Piezoelectric Materials ◽  
Geometry Optimization ◽  
Low Frequency ◽  
Substrate Thickness ◽  
Power Harvesting ◽  
Low Frequency Vibration ◽  
Length Width ◽  
Development And Utilization

The development and utilization of different structural materials, optimization of the cantilever geometry and power harvesting circuit are the most commonly methods used to increase the power density of MEMS energy harvester. This paper discusses the cantilever geometry optimization process of low power and low frequency of bimorph MEMS energy harvester. Three piezoelectric materials, ZnO, AlN and PZT are deposited on top and bottom of the cantilever Si substrate. This study focuses on the optimization of the cantilevers length, width, substrate thickness and PZe thickness in order to achieve lower than 600 Hz of resonant frequency. The harvested power for this work is in the range of 0.02 ~ 194.49 nW.

Low Voltage, Low Power Gm-C Filter for Low Frequency Applications

2018 ◽  
Vol 14 (2) ◽  
pp. 266-274 ◽  
Author(s):  
G. Hanumantha Rao ◽  
S. Rekha
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Low Frequency

scholarly journals Ultra-Low Frequency Eccentric Pendulum-Based Electromagnetic Vibrational Energy Harvester

Micromachines ◽  
2020 ◽  
Vol 11 (11) ◽  
pp. 1009
Author(s):  
Mingxue Li ◽  
Huichao Deng ◽  
Yufeng Zhang ◽  
Kexin Li ◽  
Shijie Huang ◽  
...  
Keyword(s):  
Low Power ◽  
Energy Harvester ◽  
Vibrational Energy ◽  
Low Frequency ◽  
Sensor Nodes ◽  
Wireless Sensor ◽  
Center Frequency ◽  
Vibration Energy ◽  
Outer Side ◽  
Working Frequency

With the development of low-power technology in electronic devices, the wireless sensor network shows great potential in applications in health tracing and ocean monitoring. These scenarios usually contain abundant low-frequency vibration energy, which can be collected through appropriate energy conversion architecture; thus, the common issue of limited battery life in wireless sensor devices could be solved. Traditional energy-converting structures such as the cantilever-beam type or spring-mass type have the problem of high working frequency. In this work, an eccentric pendulum-based electromagnetic vibration energy harvester is designed, analyzed, and verified with the finite element analysis method. The pendulum that contains alternative distributed magnets in the outer side works as a rotor and has the advantages of a simple structure and low center frequency. The structure size is well scalable, and the optimal output performance can be obtained by optimizing the coil thickness and width for a given diameter of the energy harvester. The simulation results show that the energy harvester could work in ultra-low frequencies of 0.2–3.0 Hz. A full-scale prototype of the energy harvester is manufactured and tested. The center working frequency is 2.0 Hz with an average output power of 8.37 mW, which has potential for application in driving low-power wireless sensor nodes.

scholarly journals A Low-Power Opamp-Less Second-Order Delta-Sigma Modulator for Bioelectrical Signals in 0.18 µm CMOS

Sensors ◽  
2021 ◽  
Vol 21 (19) ◽  
pp. 6456
Author(s):  
Fernando Cardes ◽  
Nikhita Baladari ◽  
Jihyun Lee ◽  
Andreas Hierlemann
Keyword(s):  
Low Power ◽  
Low Frequency ◽  
Cmos Technology ◽  
Low Noise ◽  
Second Order ◽  
Frequency Noise ◽  
Voltage Controlled Oscillator ◽  
Noise Shaping ◽  
Delta Sigma Modulator ◽  
Delta Sigma

This article reports on a compact and low-power CMOS readout circuit for bioelectrical signals based on a second-order delta-sigma modulator. The converter uses a voltage-controlled, oscillator-based quantizer, achieving second-order noise shaping with a single opamp-less integrator and minimal analog circuitry. A prototype has been implemented using 0.18 μm CMOS technology and includes two different variants of the same modulator topology. The main modulator has been optimized for low-noise, neural-action-potential detection in the 300 Hz–6 kHz band, with an input-referred noise of 5.0 μVrms, and occupies an area of 0.0045 mm2. An alternative configuration features a larger input stage to reduce low-frequency noise, achieving 8.7 μVrms in the 1 Hz–10 kHz band, and occupies an area of 0.006 mm2. The modulator is powered at 1.8 V with an estimated power consumption of 3.5 μW.

scholarly journals Low Power AVLS-TSPC based 2/3 Pre-Scaler

2019 ◽  
Vol 9 (1) ◽  
pp. 6687-6693
Keyword(s):  
Low Power ◽  
High Efficiency ◽  
Supply Voltage ◽  
Low Frequency ◽  
Cmos Technology ◽  
Frequency Signal ◽  
High Frequency Signal ◽  
Power Requirement ◽  
Fast Pace ◽  
Integer Division

The technology has grown at an ultra-fast pace along with the world. Small devices with less power and high efficiency are in demand. As the circuit size gets smaller, the power requirement increases due to a greater number of transistors. A pre-scaler is a circuit which reduces the high frequency signal to a low frequency signal by integer division. A new approach to low power pre-scaler is proposed in this paper, which is an add-on to the conventional pre-scaler circuit. A true single-phase clock (TSPC) circuit reduces the skew problems in the clock and is used to realize latches and flip-flops. The objective of low power is fulfilled by incorporating the Adaptive Voltage Level Source (AVLS) to TSPC based circuit. The proposed AVLS-TSPC based pre-scaler was analyzed for a frequency of 10 MHz with a supply voltage of 1.8 V for both divide by 2 and 3 modes. The proposed pre-scaler consumes considerably lesser power when compared to that of the existing pre-scaler circuit. The circuits are implemented in 180 nm CMOS technology using Cadence Virtuoso and simulated using Cadence Spectre.

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