P-38: Low-Power High-Slew-Rate CMOS Buffer Amplifier for Flat Panel Display Drivers

2006 ◽  
Vol 37 (1) ◽  
pp. 336 ◽  
Author(s):  
Sang-Kyung Kim ◽  
Young-Suk Son ◽  
Yong-Joon Jeon ◽  
Jin-Yong Jeon ◽  
Geon-Ho Lee ◽  
...  
Keyword(s):  
Low Power ◽  
Slew Rate ◽  
Flat Panel Display ◽  
Flat Panel ◽  
Buffer Amplifier

Low-power high-slew-rate CMOS buffer amplifier for flat panel display drivers

2006 ◽  
Vol 42 (4) ◽  
pp. 214 ◽  
Author(s):  
S.K. Kim ◽  
Y.-S. Son ◽  
G.H. Cho
Keyword(s):  
Low Power ◽  
Slew Rate ◽  
Flat Panel Display ◽  
Flat Panel ◽  
Buffer Amplifier

scholarly journals A High Slew Rate Buffer Amplifier Employing MTCMOS Technique for Flat Panel Display

2014 ◽  
Vol 94 (13) ◽  
pp. 30-35 ◽  
Author(s):  
Ajay Yadav ◽  
Saurabh Khandelwalb ◽  
Shyam Akashe
Keyword(s):  
Slew Rate ◽  
Flat Panel Display ◽  
Flat Panel ◽  
Buffer Amplifier

HIGH-SLEW RATE LOW-QUIESCENT CURRENT RAIL-TO-RAIL CMOS BUFFER AMPLIFIER FOR FLAT PANEL DISPLAYS

2011 ◽  
Vol 20 (07) ◽  
pp. 1277-1286 ◽  
Author(s):  
MERIH YILDIZ ◽  
SHAHRAM MINAEI ◽  
EMRE ARSLAN
Keyword(s):  
Power Supply ◽  
Monte Carlo Analysis ◽  
Cmos Process ◽  
Flat Panel Displays ◽  
Slew Rate ◽  
Flat Panel ◽  
Output Stage ◽  
Rail To Rail ◽  
Buffer Amplifier ◽  
Quiescent Current

This work presents a high-slew rate rail-to-rail buffer amplifier, which can be used for flat panel displays. The proposed buffer amplifier is composed of two transconductance amplifiers, two current comparators and a push-pull output stage. Phase compensation technique is also used to improve the phase margin value of the proposed buffer amplifier for different load capacitances. Post-layout simulations of the proposed buffer amplifier are performed using 0.35 μm AMS CMOS process parameters and 3.3 V power supply. The circuit is tested under a 600 pF capacitive load. An average settling time of 0.85 μs under a full voltage swing is obtained, while only 3 μA quiescent current is drawn from the power supply. Monte Carlo analysis is also added to show the process variation effects on the circuit.

IMPROVED LOW-POWER HIGH-SPEED BUFFER AMPLIFIER WITH SLEW-RATE ENHANCEMENT FOR LCD APPLICATIONS

2010 ◽  
Vol 19 (02) ◽  
pp. 325-334 ◽  
Author(s):  
DAVIDE MARANO ◽  
GAETANO PALUMBO ◽  
SALVATORE PENNISI
Keyword(s):  
Low Power ◽  
High Speed ◽  
Liquid Crystal Display ◽  
Slew Rate ◽  
Output Stage ◽  
Line Load ◽  
Rate Enhancement ◽  
Static Operation ◽  
Limited Power ◽  
Buffer Amplifier

The present paper addresses an improved low-power high-speed buffer amplifier topology for large-size liquid crystal display applications. The proposed buffer achieves high-speed driving performance while drawing a low quiescent current during static operation. The circuit offers enhanced slewing capabilities with a limited power consumption by exploiting a slew detector which monitors the output voltage of the input differential amplifier and outputs an additional current signal providing slew-rate enhancement at the output stage. Post-layout simulations show that the proposed buffer can drive a 1 nF column line load with 8.5 V/μs slew-rate and 0.8 μs settling time, while drawing only 8 μA static current from a 3 V power supply.

A Compact Low-Power High Slew-Rate Rail-to-Rail Class-AB Buffer Amplifier for LCD Driver ICs

2007 ◽  
Author(s):  
Jia-Hui Wang ◽  
Jing-Chuan Qiu ◽  
Hao-Yuan Zheng ◽  
Chien-Hung Tsai ◽  
Chen-Yu Wang ◽  
...  
Keyword(s):  
Low Power ◽  
Slew Rate ◽  
Class Ab ◽  
Rail To Rail ◽  
Lcd Driver ◽  
Buffer Amplifier

scholarly journals High-Speed Rail-to-Rail Class-AB Buffer Amplifier with Compact, Adaptive Biasing for FPD Applications

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2018
Author(s):  
Chang-Ho An ◽  
Bai-Sun Kong
Keyword(s):  
Low Power ◽  
Current Source ◽  
Settling Time ◽  
Output Buffer ◽  
Slew Rate ◽  
Class Ab ◽  
Tail Current ◽  
Rail To Rail ◽  
Adaptive Biasing ◽  
Buffer Amplifier

A high-slew-rate, low-power, CMOS, rail-to-rail buffer amplifier for large flat-panel-display (FPD) applications is proposed. The major circuit of the output buffer is a rail-to-rail, folded-cascode, class-AB amplifier which can control the tail current source using a compact, novel, adaptive biasing scheme. The proposed output buffer amplifier enhances the slew rate throughout the entire rail-to-rail input signal range. To obtain a high slew rate and low power consumption without increasing the static current, the tail current source of the adaptive biasing generates extra current during the transition time of the output buffer amplifier. A column driver IC incorporating the proposed buffer amplifier was fabricated in a 1.6-μm 18-V CMOS technology, whose evaluation results indicated that the static current was reduced by up to 39.2% when providing an identical settling time. The proposed amplifier also achieved up to 49.1% (90% falling) and 19.9 % (99.9% falling) improvements in terms of settling time for almost the same static current drawn and active area occupied.

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