P-20: An AMOLED Pixel for the VT Compensation of TFT and a p-Type LTPS Shift Register by Employing 1 Phase Clock Signal

2005 ◽  
Vol 36 (1) ◽  
pp. 300 ◽  
Author(s):  
Sang-Hoon Jung ◽  
Hee-Sun Shin ◽  
Jae-Hoon Lee ◽  
Min-Koo Han
Keyword(s):  
Shift Register ◽  
Clock Signal ◽  
Phase Clock ◽  
P Type

Long Life-Time Amorphous-InGaZnO TFT-Based Shift Register Using a Reset Clock Signal

2014 ◽  
Vol 35 (8) ◽  
pp. 844-846 ◽  
Author(s):  
Hoon Jeong ◽  
Byung Kook Choi ◽  
Hoon-Ju Chung ◽  
Sang Gul Lee ◽  
Yong Min Ha ◽  
...  
Keyword(s):  
Life Time ◽  
Shift Register ◽  
Clock Signal ◽  
Long Life ◽  
Amorphous Ingazno

A Full p-Type Poly-Si TFT Shift Register for Active Matrix Displays

2010 ◽  
Vol 1245 ◽  
Author(s):  
Myoung-Hoon Jung ◽  
Hoon-Ju Chung ◽  
Young-Ju Park ◽  
Ohyun Kim
Keyword(s):  
Control Method ◽  
Light Emitting Diode ◽  
Shift Register ◽  
Active Matrix ◽  
Light Emitting ◽  
Organic Light Emitting Diode ◽  
Active Matrix Displays ◽  
Output Load ◽  
Voltage Swing ◽  
P Type

AbstractA new shift register using p-type poly-Si thin-film transistors (TFTs) for active matrix display is proposed. It utilizes only p-type TFTs to simplify the fabrication process, and provides time-shifted output signals with a voltage swing from VSS to VDD without signal-level loss. In the proposed shift register, output is structurally separated from carry and therefore has a high immunity to output signal distortion caused by output load capacitance. We also propose a new light emitting control method using this shift register for high image quality active-matrix organic light emitting diode (AMOLED) displays. The proposed shift register was verified by simulation and measurement.

7.4: A Slim Border Design for Wearable Display: Using Novel P-Type Shift Register and Optimal Layout Arrangement

2015 ◽  
Vol 46 (1) ◽  
pp. 64-66 ◽  
Author(s):  
Yung-Sheng Tsai ◽  
Chun-Yen Liu ◽  
Ching-Chieh Tseng ◽  
Li-Wei Shih
Keyword(s):  
Shift Register ◽  
Optimal Layout ◽  
Type Shift ◽  
P Type

Shift register multi-phase clock based downsampled floating tap DFE for serial links

2014 ◽  
Author(s):  
Pervez M. Aziz ◽  
Hiroshi Kimura ◽  
Amaresh V. Malipatil ◽  
Shiva Kotagiri ◽  
Gordon Chan ◽  
...  
Keyword(s):  
Shift Register ◽  
Serial Links ◽  
Phase Clock ◽  
Multi Phase

Interface morphology of thermal oxide grown on polycrystalline silicon by different processes

1992 ◽  
Vol 50 (2) ◽  
pp. 1396-1397
Author(s):  
H. Yen ◽  
E. P. Kvam ◽  
R. Bashir ◽  
S. Venkatesan ◽  
G. W. Neudeck
Keyword(s):  
Integrated Circuits ◽  
Polycrystalline Silicon ◽  
Silicon Films ◽  
Interface Morphology ◽  
Oxide Interface ◽  
Poly Silicon ◽  
Thermal Oxide ◽  
Grain Orientations ◽  
Polycrystalline Silicon Films ◽  
P Type

Polycrystalline silicon, when highly doped, is commonly used in microelectronics applications such as gates and interconnects. The packing density of integrated circuits can be enhanced by fabricating multilevel polycrystalline silicon films separated by insulating SiO2 layers. It has been found that device performance and electrical properties are strongly affected by the interface morphology between polycrystalline silicon and SiO2. As a thermal oxide layer is grown, the poly silicon is consumed, and there is a volume expansion of the oxide relative to the atomic silicon. Roughness at the poly silicon/thermal oxide interface can be severely deleterious due to stresses induced by the volume change during oxidation. Further, grain orientations and grain boundaries may alter oxidation kinetics, which will also affect roughness, and thus stress.Three groups of polycrystalline silicon films were deposited by LPCVD after growing thermal oxide on p-type wafers. The films were doped with phosphorus or arsenic by three different methods.

Determination of arsenic atom distribution arsenic doped silicon using HOLZ-line analysis

1996 ◽  
Vol 54 ◽  
pp. 976-977
Author(s):  
Y. Kikuchi ◽  
N. Hashikawa ◽  
F. Uesugi ◽  
E. Wakai ◽  
K. Watanabe ◽  
...  
Keyword(s):  
Inelastic Scattering ◽  
Zone Axis ◽  
Experimental Result ◽  
Background Intensity ◽  
Crystal Thickness ◽  
Arsenic Atom ◽  
Doped Silicon ◽  
P Type ◽  
Line Analysis

In order to measure the concentration of arsenic atoms in nanometer regions of arsenic doped silicon, the HOLZ analysis is carried out underthe exact [011] zone axis observation. In previous papers, it is revealed that the position of two bright lines in the outer SOLZ structures on the[011] zone axis is little influenced by the crystal thickness and the background intensity caused by inelastic scattering electrons, but is sensitive to the concentration of As atoms substitutbnal for Siatomic site.As the result, it becomes possible to determine the concentration of electrically activated As atoms in silicon within an observed area by means of the simple fitting between experimental result and dynamical simulatioan. In the present work, in order to investigate the distribution of electrically activated As in silicon, the outer HOLZ analysis is applied using a nanometer sized probe of TEM equipped with a FEG.Czodiralsld-gown<100>orientated p-type Si wafers with a resistivity of 10 Ώ cm are used for the experiments.TheAs+ implantation is performed at a dose of 5.0X1015cm-2at 25keV.

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