scholarly journals Selection of the Optimal IGBT Blocking Voltage for Electric Drives based on Modular Multilevel Converter

2020 ◽  
Vol 25 (4) ◽  
pp. 1-10
Author(s):  
Paulo R. M. Júnior ◽  
João Victor Matos Farias ◽  
Allan Fagner Cupertino ◽  
Gabriel A. Mendonça ◽  
Marcelo M. Stopa ◽  
...  
Keyword(s):  
Modular Multilevel Converter ◽  
Multilevel Converter ◽  
Electric Drives ◽  
Blocking Voltage ◽  
Selection Of

Modular Multilevel Converter Based Topology for High-Speed, Low-Voltage Electric Drives

2020 ◽  
Vol 56 (5) ◽  
pp. 5202-5211
Author(s):  
Luca Tarisciotti ◽  
Alessandro Costabeber ◽  
Francesco Tardelli ◽  
Roberto Cardenas
Keyword(s):  
High Speed ◽  
Low Voltage ◽  
Modular Multilevel Converter ◽  
Multilevel Converter ◽  
Electric Drives

scholarly journals A Multilevel Inverter Topology Using Diode Half-Bridge Circuit with Reduced Power Component

Energies ◽  
2021 ◽  
Vol 14 (21) ◽  
pp. 7249
Author(s):  
Jagabar Sathik ◽  
Shady H. E. Abdel Aleem ◽  
Rasoul Shalchi Alishah ◽  
Dhafer Almakhles ◽  
Kent Bertilsson ◽  
...  
Keyword(s):  
Comparative Analysis ◽  
Optimal Topology ◽  
Multilevel Converter ◽  
Medium Voltage ◽  
Asymmetric Structures ◽  
Blocking Voltage ◽  
Minimum Number ◽  
Simulation Results ◽  
Inverter Topology ◽  
Selection Of

This paper presents a new multilevel converter with a reduced number of power components for medium voltage applications. Both symmetric and asymmetric structures of the presented multilevel converter are proposed. The symmetric topology requires equal dc source values, whereas the asymmetric topology uses minimum switch count. However, both structures suffer from high blocking voltage across the switches. To reduce the blocking voltage on switches, an optimal topology is presented and analyzed for the selection of the minimum number of switches and dc sources, while maintaining a low blocking voltage across the switches. A comparative analysis with recently published topologies was performed. The simulation results, as well as the comparative analysis, validated the robustness and effectiveness of the proposed topology in terms of the reduced power loss, lowered number of components, and cost. Furthermore, in addition to the simulation results, the performance of the proposed topology was verified using experimental results of 9, 17, and 25 levels.

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