scholarly journals Analysis on the Centroid Offset of Coupling Beam in Array-composite Resonator due to Process Variations

2018 ◽  
Vol 30 (11) ◽  
pp. 2727
Author(s):  
Haixia Yan ◽  
Jiaping Tao ◽  
Linxi Dong
Keyword(s):  
Process Variations ◽  
Coupling Beam ◽  
Composite Resonator

Pseudo-Dynamic Fault Isolation Technique Using Backside Emission Microscopy – Case Study, Where All Other Methods Fail

2002 ◽  
Author(s):  
Yoav Weizman ◽  
Ezra Baruch ◽  
Michael Zimin
Keyword(s):  
Failure Analysis ◽  
Process Variations ◽  
Fault Isolation ◽  
Operating Conditions ◽  
Detection Sensitivity ◽  
Isolation Technique ◽  
Root Cause ◽  
Emission Microscopy ◽  
Failure Location ◽  
Noisy Background

Abstract Emission microscopy is usually implemented for static operating conditions of the DUT. Under dynamic operation it is nearly impossible to identify a failure out of the noisy background. In this paper we describe a simple technique that could be used in cases where the temporal location of the failure was identified however the physical location is not known or partially known. The technique was originally introduced to investigate IDDq failures (1) in order to investigate timing related issues with automated tester equipment. Ishii et al (2) improved the technique and coupled an emission microscope to the tester for functional failure analysis of DRAMs and logic LSIs. Using consecutive step-by-step tester halting coupled to a sensitive emission microscope, one is able detect the failure while it occurs. We will describe a failure analysis case in which marginal design and process variations combined to create contention at certain logic states. Since the failure occurred arbitrarily, the use of the traditional LVP, that requires a stable failure, misled the analysts. Furthermore, even if we used advanced tools as PICA, which was actually designed to locate such failures, we believe that there would have been little chance of observing the failure since the failure appeared only below 1.3V where the PICA tool has diminished photon detection sensitivity. For this case the step-by-step halting technique helped to isolate the failure location after a short round of measurements. With the use of logic simulations, the root cause of the failure was clear once the failing gate was known.

Analysis of Process Variations in W-Band GaN MMIC PAs Using Nonparametric Statistics

2021 ◽  
Vol 69 (4) ◽  
pp. 2304-2318
Author(s):  
Shane Verploegh ◽  
Mauricio Pinto ◽  
Laila Marzall ◽  
Daniel Martin ◽  
Gregor Lasser ◽  
...  
Keyword(s):  
Process Variations ◽  
Nonparametric Statistics ◽  
W Band

scholarly journals Power Management of Monolithic 3D Manycore Chips with Inter-tier Process Variations

2021 ◽  
Vol 17 (2) ◽  
pp. 1-19
Author(s):  
Anwesha Chatterjee ◽  
Shouvik Musavvir ◽  
Ryan Gary Kim ◽  
Janardhan Rao Doppa ◽  
Partha Pratim Pande
Keyword(s):  
Power Management ◽  
Process Variations

Design of a Robust Memristive Spiking Neuromorphic System with Unsupervised Learning in Hardware

2021 ◽  
Vol 17 (4) ◽  
pp. 1-26
Author(s):  
Md Musabbir Adnan ◽  
Sagarvarma Sayyaparaju ◽  
Samuel D. Brown ◽  
Mst Shamim Ara Shawkat ◽  
Catherine D. Schuman ◽  
...  
Keyword(s):  
Unsupervised Learning ◽  
Recognition Task ◽  
Single Layer ◽  
Process Variations ◽  
Spike Timing ◽  
System Level ◽  
Design Parameters ◽  
Digital Pulse ◽  
Neuromorphic System ◽  
The Impact

Spiking neural networks (SNN) offer a power efficient, biologically plausible learning paradigm by encoding information into spikes. The discovery of the memristor has accelerated the progress of spiking neuromorphic systems, as the intrinsic plasticity of the device makes it an ideal candidate to mimic a biological synapse. Despite providing a nanoscale form factor, non-volatility, and low-power operation, memristors suffer from device-level non-idealities, which impact system-level performance. To address these issues, this article presents a memristive crossbar-based neuromorphic system using unsupervised learning with twin-memristor synapses, fully digital pulse width modulated spike-timing-dependent plasticity, and homeostasis neurons. The implemented single-layer SNN was applied to a pattern-recognition task of classifying handwritten-digits. The performance of the system was analyzed by varying design parameters such as number of training epochs, neurons, and capacitors. Furthermore, the impact of memristor device non-idealities, such as device-switching mismatch, aging, failure, and process variations, were investigated and the resilience of the proposed system was demonstrated.

scholarly journals An Automatic Offset Calibration Method for Differential Charge-Based Capacitance Measurement

2021 ◽  
Vol 11 (2) ◽  
pp. 22
Author(s):  
Umberto Ferlito ◽  
Alfio Dario Grasso ◽  
Michele Vaiana ◽  
Giuseppe Bruno
Keyword(s):  
Standard Deviation ◽  
Output Voltage ◽  
Process Variations ◽  
Calibration Method ◽  
Capacitance Measurement ◽  
Effective Technique ◽  
Fully Integrated ◽  
Front End ◽  
Novel Method ◽  
On Chip

Charge-Based Capacitance Measurement (CBCM) technique is a simple but effective technique for measuring capacitance values down to the attofarad level. However, when adopted for fully on-chip implementation, this technique suffers output offset caused by mismatches and process variations. This paper introduces a novel method that compensates the offset of a fully integrated differential CBCM electronic front-end. After a detailed theoretical analysis of the differential CBCM topology, we present and discuss a modified architecture that compensates mismatches and increases robustness against mismatches and process variations. The proposed circuit has been simulated using a standard 130-nm technology and shows a sensitivity of 1.3 mV/aF and a 20× reduction of the standard deviation of the differential output voltage as compared to the traditional solution.

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