scholarly journals Software Protection via Composable Process-level Virtual Machines

2013 ◽  
Author(s):  
Sudeep Ghosh
Keyword(s):  
Virtual Machines ◽  
Software Protection ◽  
Process Level

Implementing Distributed, Self-Managing Computing Services Infrastructure using a Scalable, Parallel and Network-Centric Computing Model

2012 ◽  
pp. 57-78 ◽  
Author(s):  
Rao Mikkilineni ◽  
Giovanni Morana ◽  
Ian Seyler
Keyword(s):  
Cloud Computing ◽  
Network Architecture ◽  
Virtual Machines ◽  
Von Neumann ◽  
Accounting Performance ◽  
Computing Model ◽  
Computing Services ◽  
Many Core ◽  
Distributed Cloud ◽  
Process Level

This chapter introduces a new network-centric computing model using Distributed Intelligent Managed Element (DIME) network architecture (DNA). A parallel signaling network overlay over a network of self-managed von Neumann computing nodes is utilized to implement dynamic fault, configuration, accounting, performance, and security management of both the nodes and the network based on business priorities, workload variations and latency constraints. Two implementations of the new computing model are described which demonstrate the feasibility of the new computing model. One implementation provides service virtualization at the Linux process level and another provides virtualization of a core in a many-core processor. Both point to an alternative way to assure end-to-end transaction reliability, availability, performance, and security in distributed Cloud computing, reducing current complexity in configuring and managing virtual machines and making the implementation of Federation of Clouds simpler.

Task Scheduling Algorithm based on Resources Segregation in Cloud Environment

2018 ◽  
pp. 96-101
Author(s):  
Shailendra Raghuvanshi ◽  
Priyanka Dubey
Keyword(s):  
Load Balancing ◽  
Task Scheduling ◽  
Waiting Time ◽  
Virtual Machines ◽  
Scheduling Algorithm ◽  
Cloud Environment ◽  
Task Scheduling Algorithm ◽  
Machine Utilization ◽  
Independent Tasks ◽  
Optimal Machine

Load balancing of non-preemptive independent tasks on virtual machines (VMs) is an important aspect of task scheduling in clouds. Whenever certain VMs are overloaded and remaining VMs are under loaded with tasks for processing, the load has to be balanced to achieve optimal machine utilization. In this paper, we propose an algorithm named honey bee behavior inspired load balancing, which aims to achieve well balanced load across virtual machines for maximizing the throughput. The proposed algorithm also balances the priorities of tasks on the machines in such a way that the amount of waiting time of the tasks in the queue is minimal. We have compared the proposed algorithm with existing load balancing and scheduling algorithms. The experimental results show that the algorithm is effective when compared with existing algorithms. Our approach illustrates that there is a significant improvement in average execution time and reduction in waiting time of tasks on queue using workflowsim simulator in JAVA.

Conceptual model of choice of hardware and software protection

2020 ◽  
Vol 7 (1) ◽  
pp. 63-71
Author(s):  
Yaroslav E. Prokushev ◽  
◽  
Julia V. Maliy ◽  
Keyword(s):  
Conceptual Model ◽  
Software Protection

Manufacturing In-Line Whole Wafer Focused Ion Beam (FIB) Memory Address Descramble Verification

2008 ◽  
Author(s):  
Steven B. Herschbein ◽  
Hyoung H. Kang ◽  
Scott L. Jansen ◽  
Andrew S. Dalton
Keyword(s):  
Flip Chip ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Random Access ◽  
Cell Counting ◽  
Test Results ◽  
Laboratory Procedure ◽  
Memory Array ◽  
Dual Beam ◽  
Process Level

Abstract Test engineers and failure analyst familiar with random access memory arrays have probably encountered the frustration of dealing with address descrambling. The resulting nonsequential internal bit cell counting scheme often means that the location of the failing cell under investigation is nowhere near where it is expected to be. A logical to physical algorithm for decoding the standard library block might have been provided with the design, but is it still correct now that the array has been halved and inverted to fit the available space in a new processor chip? Off-line labs have traditionally been tasked with array layout verification. In the past, hard and soft failures could be induced on the frontside of finished product, then bitmapped to see if the sites were in agreement. As density tightened, flip-chip FIB techniques to induce a pattern of hard fails on packaged devices came into practice. While the backside FIB edit method is effective, it is complex and expensive. The installation of an in-line Dual Beam FIB created new opportunities to move FA tasks out of the lab and into the FAB. Using a new edit procedure, selected wafers have an extensive pattern of defects 'written' directly into the memory array at an early process level. Bitmapping of the RAM blocks upon wafer completion is then used to verify correlation between the physical damaged cells and the logical sites called out in the test results. This early feedback in-line methodology has worked so well that it has almost entirely displaced the complex laboratory procedure of backside FIB memory array descramble verification.

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