Evaluations of electronic neuron model for low power VLSI implementation

Evaluations of Electronic Neuron Model for Low Power VLSI Implementation

2019 International SoC Design Conference (ISOCC) ◽

10.1109/isocc47750.2019.9027702 ◽

2019 ◽

Author(s):

Yixuan He ◽

Kyung Ki Kim ◽

Yong-Bin Kim

Keyword(s):

Low Power ◽

Neuron Model ◽

Vlsi Implementation ◽

Electronic Neuron

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A new neuron model suitable for low power VLSI implementation

2015 9th International Conference on Electrical and Electronics Engineering (ELECO) ◽

10.1109/eleco.2015.7394550 ◽

2015 ◽

Author(s):

Ozgur Erdener ◽

Serdar Ozoguz

Keyword(s):

Low Power ◽

Neuron Model ◽

Vlsi Implementation

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A low power VLSI implementation of the Izhikevich neuron model

2011 IEEE 9th International New Circuits and systems conference ◽

10.1109/newcas.2011.5981282 ◽

2011 ◽

Cited By ~ 7

Author(s):

A. Samil Demirkol ◽

Serdar Ozoguz

Keyword(s):

Low Power ◽

Neuron Model ◽

Vlsi Implementation ◽

Izhikevich Neuron Model

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VLSI Implementation of High Speed-Low Power-Area Efficient Multiplier Using Modified Vedic Mathematical Techniques

Recent Patents on Computer Science ◽

10.2174/2213275908666150220203501 ◽

2017 ◽

Vol 9 (3) ◽

pp. 216-221

Author(s):

Abdul Kareem ◽

Vardhana M. ◽

Praveen Kumar

Keyword(s):

Low Power ◽

High Speed ◽

Vlsi Implementation ◽

Mathematical Techniques ◽

Area Efficient

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Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering

2004 IEEE International Conference on Acoustics, Speech, and Signal Processing ◽

10.1109/icassp.2004.1327056 ◽

2004 ◽

Author(s):

Yongtao Wang ◽

H. Mahmoodi ◽

Lih-Yih Chiou ◽

Hunsoo Choo ◽

Jongsun Park ◽

...

Keyword(s):

Low Power ◽

Adaptive Filtering ◽

High Performance ◽

Hardware Architecture ◽

Vlsi Implementation ◽

Polyphase Channelizer

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Low-Voltage Low-Power Integrable CMOS Circuit Implementation of Integer- and Fractional–Order FitzHugh–Nagumo Neuron Model

IEEE Transactions on Neural Networks and Learning Systems ◽

10.1109/tnnls.2018.2877454 ◽

2019 ◽

Vol 30 (7) ◽

pp. 2108-2122 ◽

Cited By ~ 6

Author(s):

Farooq Ahmad Khanday ◽

Nasir Ali Kant ◽

Mohammad Rafiq Dar ◽

Tun Zainal Azni Zulkifli ◽

Costas Psychalinos

Keyword(s):

Low Power ◽

Fractional Order ◽

Neuron Model ◽

Low Voltage ◽

Cmos Circuit ◽

Circuit Implementation

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VLSI Implementation of Low-Power and High-SFDR Digital Frequency Synthesizer for Underwater Instruments and Network Systems

Springer Proceedings in Physics - Advanced Materials ◽

10.1007/978-3-319-03749-3_23 ◽

2014 ◽

pp. 289-304

Author(s):

Ying-Shen Juang ◽

Tze-Yun Sung ◽

Hsi-Chin Hsin

Keyword(s):

Low Power ◽

Frequency Synthesizer ◽

Vlsi Implementation ◽

Network Systems ◽

Digital Frequency

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Asynchronous low power VLSI implementation of the International Data Encryption Algorithm

ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) ◽

10.1109/icecs.2001.957482 ◽

2002 ◽

Cited By ~ 3

Author(s):

N. Sklavos ◽

O. Koufopavlou

Keyword(s):

Low Power ◽

Data Encryption ◽

Vlsi Implementation ◽

Encryption Algorithm ◽

International Data

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A VLSI Implementation of Low Power, Low Data Rate UWB Transceiver for Location and Tracking Applications

The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology ◽

10.1007/s11265-006-7279-x ◽

2006 ◽

Vol 43 (1) ◽

pp. 43-58 ◽

Cited By ~ 6

Author(s):

Sakari Tiuraniemi ◽

Lucian Stoica ◽

Alberto Rabbachin ◽

Ian Oppermann

Keyword(s):

Low Power ◽

Data Rate ◽

Vlsi Implementation

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VLSI implementation of a low-power antilogarithmic converter

IEEE Transactions on Computers ◽

10.1109/tc.2003.1228517 ◽

2003 ◽

Vol 52 (9) ◽

pp. 1221-1228 ◽

Cited By ~ 44

Author(s):

K.H. Abed ◽

R.E. Siferd

Keyword(s):

Low Power ◽

Vlsi Implementation

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