From sequencing to hardware acceleration of DNA alignment software: A integral review

2015 ◽  
Vol 36 (3) ◽  
pp. 257-275 ◽  
Author(s):  
D Pacheco Bautista ◽  
M González Pérez ◽  
I Algredo Badillo
Keyword(s):  
Hardware Acceleration ◽  
Dna Alignment

Bit-Vector-Based Hardware Accelerator for DNA Alignment Tools

2020 ◽  
pp. 2150087
Author(s):  
Daniel Pacheco Bautista ◽  
Ricardo Carreño Aguilera ◽  
Francisco Aguilar Acevedo ◽  
Ignacio Algredo Badillo
Keyword(s):  
Dna Analysis ◽  
Modular Design ◽  
Hardware Acceleration ◽  
Sequencing Technologies ◽  
Analysis Process ◽  
Alignment System ◽  
Bit Vector ◽  
Dna Alignment ◽  
Reference Genomes ◽  
Generation Sequencing

Next generation sequencing technologies have noticeably improved in the last decade. Time and cost of whole genome sequencing are important challenges that must be reduced, opening unprecedented opportunities to various research and development areas. The alignment or mapping of small reads produced by sequencing machines to reference genomes of billions of nucleotides is a fundamental task in this sequencing process. It is computationally highly demanding and has become the bottleneck of the DNA analysis process. This paper proposes hardware acceleration based on FPGA of the Myers bit-parallelized algorithm, appropriately modified to be used in the extend stage of DNA alignment tools. The proposed design can be employed in conjunction with software functions, as it constitutes an extremely fast heterogeneous DNA alignment system. The implementation results show a speedup of up to [Formula: see text] relative to a sequential implementation only in software. In addition, due to the limited use of FPGA resources and the modular design, multiple modules can be used to completely populate the chip, further increasing the computing speed.

Hardware Acceleration of Bilateral Filters

2013 ◽  
Vol 133 (2) ◽  
pp. 132-138
Author(s):  
Shuhei Isa ◽  
Chikatoshi Yamada ◽  
Yasunori Nagata
Keyword(s):  
Hardware Acceleration ◽  
Bilateral Filters

The real-time computing of the Stirling formula based on hardware acceleration

2013 ◽  
Author(s):  
Jiyang Yu ◽  
Dan Huang ◽  
Siyang Zhao ◽  
Nan Pei ◽  
Huixia Cheng ◽  
...  
Keyword(s):  
Real Time ◽  
Hardware Acceleration ◽  
Stirling Formula ◽  
The Real ◽  
Real Time Computing

Design and Implementation of Low Energy Wireless Network Nodes based on Hardware Compression Acceleration

2019 ◽  
Vol 12 ◽  
Author(s):  
Hui Yang ◽  
Anand Nayyar
Keyword(s):  
Energy Consumption ◽  
Data Compression ◽  
Energy Saving ◽  
Optimization Design ◽  
Hardware Acceleration ◽  
Transmission Efficiency ◽  
General Purpose ◽  
Storage Space ◽  
General Purpose Processor ◽  
Compression Time

: In the fast development of information, the information data is increasing in geometric multiples, and the speed of information transmission and storage space are required to be higher. In order to reduce the use of storage space and further improve the transmission efficiency of data, data need to be compressed. processing. In the process of data compression, it is very important to ensure the lossless nature of data, and lossless data compression algorithms appear. The gradual optimization design of the algorithm can often achieve the energy-saving optimization of data compression. Similarly, The effect of energy saving can also be obtained by improving the hardware structure of node. In this paper, a new structure is designed for sensor node, which adopts hardware acceleration, and the data compression module is separated from the node microprocessor.On the basis of the ASIC design of the algorithm, by introducing hardware acceleration, the energy consumption of the compressed data was successfully reduced, and the proportion of energy consumption and compression time saved by the general-purpose processor was as high as 98.4 % and 95.8 %, respectively. It greatly reduces the compression time and energy consumption.

Accelerating Genomic Data Analytics with Composable Hardware Acceleration Framework

IEEE Micro ◽  
2021 ◽  
pp. 1-1
Author(s):  
Tae Jun Ham ◽  
David Bruns-Smith ◽  
Brendan Sweeney ◽  
Yejin Lee ◽  
Seong Hoon Seo ◽  
...  
Keyword(s):  
Data Analytics ◽  
Genomic Data ◽  
Hardware Acceleration

High-Performance Image Filters via Sparse Approximations

2020 ◽  
Vol 3 (2) ◽  
pp. 1-19
Author(s):  
Kersten Schuster ◽  
Philip Trettner ◽  
Leif Kobbelt
Keyword(s):  
High Performance ◽  
Hardware Acceleration ◽  
Optimization Method ◽  
Translation Invariant ◽  
Approximation Quality ◽  
Trade Offs ◽  
Sparse Approximations ◽  
Image Filters ◽  
Good Trade ◽  
And Performance

We present a numerical optimization method to find highly efficient (sparse) approximations for convolutional image filters. Using a modified parallel tempering approach, we solve a constrained optimization that maximizes approximation quality while strictly staying within a user-prescribed performance budget. The results are multi-pass filters where each pass computes a weighted sum of bilinearly interpolated sparse image samples, exploiting hardware acceleration on the GPU. We systematically decompose the target filter into a series of sparse convolutions, trying to find good trade-offs between approximation quality and performance. Since our sparse filters are linear and translation-invariant, they do not exhibit the aliasing and temporal coherence issues that often appear in filters working on image pyramids. We show several applications, ranging from simple Gaussian or box blurs to the emulation of sophisticated Bokeh effects with user-provided masks. Our filters achieve high performance as well as high quality, often providing significant speed-up at acceptable quality even for separable filters. The optimized filters can be baked into shaders and used as a drop-in replacement for filtering tasks in image processing or rendering pipelines.

Sign in / Sign up

Export Citation Format

Share Document