Forced Convection 4 (Channel Flow)

1974 ◽  
Author(s):  
Zoran Zaric
Keyword(s):  
Forced Convection ◽  
Channel Flow

Thermal Equilibrium in Transient Forced Convection Porous Channel Flow

2004 ◽  
Vol 57 (1) ◽  
pp. 49-58 ◽  
Author(s):  
B. A. Abu-Hijleh ◽  
M. A. Al-Nimr ◽  
M. A. Hader
Keyword(s):  
Forced Convection ◽  
Channel Flow ◽  
Thermal Equilibrium ◽  
Porous Channel

Multidisciplinary Placement Optimization of Heat Generating Electronic Components on Printed Circuit Board in Channel Flow Forced Convection Using Artificial Neural Networks

2005 ◽  
Author(s):  
Tohru Suwa ◽  
Hamid Hadim
Keyword(s):  
Neural Networks ◽  
Heat Flux ◽  
Artificial Neural Networks ◽  
Forced Convection ◽  
Channel Flow ◽  
Superposition Method ◽  
Electronic Components ◽  
Printed Circuit ◽  
Placement Optimization ◽  
Optimization Methodology

A multidisciplinary placement optimization methodology for heat generating electronic components on printed circuit boards (PCBs) in channel flow forced convection is presented. In this methodology, thermal, electrical, and placement criteria involving junction temperature, wiring density, line length for high frequency signals, and critical component location are optimized simultaneously using the genetic algorithm. A board-level thermal performance prediction methodology based on channel flow forced convection boundary conditions is developed. The methodology consists of a combination of artificial neural networks (ANNs) and a superposition method that is able to predict PCB surface and component junction temperatures in a much shorter calculation time than the existing numerical methods. Three ANNs are used for predicting temperature rise at the PCB surface caused by a single heat flux at an arbitrary location on the board, while temperature rise due to multiple heat flux is calculated using a superposition method. Compact thermal models are used for the electronic components thermal modeling. Using this optimization methodology, large calculation time reduction is achieved without losing accuracy. For thermal model validation, the present thermal methodology predicts junction temperatures with maximum error of 1.8°C comparing to the conjugate solid/ fluid heat transfer analysis result. The present thermal modeling takes 12 seconds, while the conjugate analysis takes 30 hours for the validation on the same computer. To demonstrate the capabilities of the present methodology, a test case of component placement on a PCB is presented.

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