Efficient CORDIC-Based Processing Elements in Scalable Complex Matrix Inversion

2014 ◽  
Vol E97.A (5) ◽  
pp. 1144-1148
Author(s):  
Huan HE ◽  
Feng YU ◽  
Bei ZHAO
Keyword(s):  
Matrix Inversion ◽  
Complex Matrix ◽  
Processing Elements

scholarly journals Floating Point versus Fixed point Tradeoffs in FPGA Implementations of QR Decomposition Algorithm

2019 ◽  
Vol 3 (5) ◽  
Author(s):  
Siavash Amin-Nejad ◽  
Katayoon Basharkhah ◽  
Tayyebeh Asgari Gashteroodkhani
Keyword(s):  
Communication Systems ◽  
Qr Decomposition ◽  
Matrix Inversion ◽  
Floating Point ◽  
Clock Frequency ◽  
Complex Matrix ◽  
Vector Processing ◽  
Point Versus ◽  
Digital Communication Systems ◽  
Processing Architecture

A wide variety of digital communication systems are encountered with high computational tasks. QR decomposition is one of such algorithms that can be implemented on FPGAs as a solution to large complex matrix inversion problems. A flexible vector processing architecture for the fixed and floating point implementations of the QR decomposition is presented. The design is implemented on the StratixIV device with 230K logic elements and verified with the SignalTap II built-in logic analyzer. Throughputs of 2.4M and 2.11M decompositions per second with maximum clock frequency of 340 MHz and 360 MHz are achieved for 4×4 matrices with the fixed and floating point designs respectively. The FPGA resource utilizations of the two data type implementations are also compared for different matrix sizes for the StratixIV and Arria10 devices.

Sign in / Sign up

Export Citation Format

Share Document