Bit-Plane Coding of Lattice Codevectors

2013 ◽  
Vol E96.A (8) ◽  
pp. 1817-1820 ◽  
Author(s):  
Wisarn PATCHOO ◽  
Thomas R. FISCHER
Keyword(s):  
Bit Plane Coding ◽  
Bit Plane

Bit-Plane Coding in Extractable Source Coding: optimality, modeling, and application to 360° data

2021 ◽  
pp. 1-1
Author(s):  
Fangping Ye ◽  
Navid Mahmoudian Bidgoli ◽  
Elsa Dupraz ◽  
Aline Roumy ◽  
Karine Amis ◽  
...  
Keyword(s):  
Source Coding ◽  
Bit Plane Coding ◽  
Bit Plane

Image compression using bit-plane coding of wavelet coefficients

1996 ◽  
Vol 32 (19) ◽  
pp. 1773 ◽  
Author(s):  
K. Nguyen-Phi ◽  
H. Weinrichter
Keyword(s):  
Image Compression ◽  
Wavelet Coefficients ◽  
Bit Plane Coding ◽  
Bit Plane

High-Performance Low-Complexity Bit-Plane Coding Scheme for MPEG-4 FGS

2005 ◽  
Author(s):  
Hong-Yu Chao ◽  
Jia-Shung Wang ◽  
Juin-Long Lin ◽  
Kai-Chao Yang ◽  
Chien-Ming Wu ◽  
...  
Keyword(s):  
High Performance ◽  
Low Complexity ◽  
Coding Scheme ◽  
Bit Plane Coding ◽  
Bit Plane

High Throughput VLSI Architecture of MQ-Coder for JPEG2000

2011 ◽  
Vol 403-408 ◽  
pp. 2321-2324
Author(s):  
Jiang Yi Shi ◽  
Jie Pang ◽  
Zhi Xiong Di ◽  
Yao Hui Liu ◽  
Yun Song Li
Keyword(s):  
High Throughput ◽  
Clock Cycle ◽  
Parallel Architecture ◽  
Vlsi Architecture ◽  
Bit Plane Coding ◽  
Bit Plane

In this paper, a design of high throughput VLSI architecture of MQ-Coder is proposed. Usually, because the regular operation of the MQ-Coder is sequential, the coding speed will be bottlenecked at the interface between the output of the Bit-Plane coding and the input of the MQ-Coder. Therefore, the proposed MQ-Coder architecture can process two symbols for each clock cycle. The main characteristics are the prediction of index, the simplified condition of renormalization, and the partly parallel architecture in renormalization. From synthesis results of the DC tools, using the TSMC 0.18 μm technology library, the frequency can reach 285.4MHz, which is comparable to that of other architectures and suitable for chip implementation.

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