Bidirectional Limited-Magnitude Error Correction Codes for Flash Memories

2013 ◽  
Vol E96.A (7) ◽  
pp. 1602-1608 ◽  
Author(s):  
Myeongwoon JEON ◽  
Jungwoo LEE
Keyword(s):  
Error Correction ◽  
Error Correction Codes ◽  
Flash Memories

scholarly journals Deep PUF: A Highly Reliable DRAM PUF-Based Authentication for IoT Networks Using Deep Convolutional Neural Networks

Sensors ◽  
2021 ◽  
Vol 21 (6) ◽  
pp. 2009
Author(s):  
Fatemeh Najafi ◽  
Masoud Kaveh ◽  
Diego Martín ◽  
Mohammad Reza Mosavi
Keyword(s):  
Error Correction ◽  
Random Access ◽  
Error Correction Codes ◽  
Access Memory ◽  
Deep Convolutional Neural Networks ◽  
Device Identification ◽  
Physical Unclonable Functions ◽  
Server Side ◽  
Correction Technique ◽  
Reduction Methods

Traditional authentication techniques, such as cryptographic solutions, are vulnerable to various attacks occurring on session keys and data. Physical unclonable functions (PUFs) such as dynamic random access memory (DRAM)-based PUFs are introduced as promising security blocks to enable cryptography and authentication services. However, PUFs are often sensitive to internal and external noises, which cause reliability issues. The requirement of additional robustness and reliability leads to the involvement of error-reduction methods such as error correction codes (ECCs) and pre-selection schemes that cause considerable extra overheads. In this paper, we propose deep PUF: a deep convolutional neural network (CNN)-based scheme using the latency-based DRAM PUFs without the need for any additional error correction technique. The proposed framework provides a higher number of challenge-response pairs (CRPs) by eliminating the pre-selection and filtering mechanisms. The entire complexity of device identification is moved to the server side that enables the authentication of resource-constrained nodes. The experimental results from a 1Gb DDR3 show that the responses under varying conditions can be classified with at least a 94.9% accuracy rate by using CNN. After applying the proposed authentication steps to the classification results, we show that the probability of identification error can be drastically reduced, which leads to a highly reliable authentication.

Shannon capacities and error-correction codes for optical atmospheric turbulent channels

2005 ◽  
Vol 4 (9) ◽  
pp. 586 ◽  
Author(s):  
Jaime A. Anguita ◽  
Ivan B. Djordjevic ◽  
Mark A. Neifeld ◽  
Bane V. Vasic
Keyword(s):  
Error Correction ◽  
Error Correction Codes

scholarly journals Exponential Golomb and Rice Error Correction Codes for Generalized Near-Capacity Joint Source and Channel Coding

IEEE Access ◽  
2016 ◽  
Vol 4 ◽  
pp. 7154-7175 ◽  
Author(s):  
Matthew F. Brejza ◽  
Tao Wang ◽  
Wenbo Zhang ◽  
David Al-Khalili ◽  
Robert G. Maunder ◽  
...  
Keyword(s):  
Error Correction ◽  
Channel Coding ◽  
Error Correction Codes

A 10T Cell Design without Half Select Problem for Bit-Interleaving Architecture in 65nm CMOS

2013 ◽  
Vol 373-375 ◽  
pp. 1607-1611
Author(s):  
Hong Gang Zhou ◽  
Shou Biao Tan ◽  
Qiang Song ◽  
Chun Yu Peng
Keyword(s):  
Error Correction ◽  
Low Voltage ◽  
Cmos Technology ◽  
Soft Error ◽  
Error Correction Codes ◽  
Cell Design ◽  
Low Voltage Operation ◽  
Sram Cell ◽  
Simulation Results ◽  
Nanometer Regime

With the scaling of process technologies into the nanometer regime, multiple-bit soft error problem becomes more serious. In order to improve the reliability and yield of SRAM, bit-interleaving architecture which integrated with error correction codes (ECC) is commonly used. However, this leads to the half select problem, which involves two aspects: the half select disturb and the additional power caused by half-selected cells. In this paper, we propose a new 10T cell to allow the bit-interleaving array while completely eliminating the half select problem, thus allowing low-power and low-voltage operation. In addition, the RSNM and WM of our proposed 10T cell are improved by 21% and nearly one times, respectively, as compared to the conventional 6T SRAM cell in SMIC 65nm CMOS technology. We also conduct a comparison with the conventional 6T cell about the leakage simulation results, which show 14% of leakage saving in the proposed 10T cell.

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