A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology

2010 ◽  
Vol E93-A (12) ◽  
pp. 2456-2462 ◽  
Author(s):  
Xiaolei ZHU ◽  
Yanfei CHEN ◽  
Masaya KIBUNE ◽  
Yasumoto TOMITA ◽  
Takayuki HAMADA ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Control Technique ◽  
Scaled Cmos

A dynamic offset control technique for comparator design in scaled CMOS technology

2008 ◽  
Author(s):  
Xiaolei Zhu ◽  
Yanfei Chen ◽  
Masaya Kibune ◽  
Yasumoto Tomita ◽  
Takayuki Hamada ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Control Technique ◽  
Scaled Cmos

Scaled CMOS technology using SEG isolation and buried well process

1986 ◽  
Vol 33 (11) ◽  
pp. 1659-1666 ◽  
Author(s):  
Nobuhiro Endo ◽  
N. Kasai ◽  
A. Ishitani ◽  
H. Kitajima ◽  
Y. Kurogi
Keyword(s):  
Cmos Technology ◽  
Scaled Cmos

A Power-Enhanced Active Rectifier with Offset-Controlled Comparator for Self-Powered PEH Systems

2018 ◽  
Vol 27 (05) ◽  
pp. 1850079 ◽  
Author(s):  
Lianxi Liu ◽  
Yanbo Pang ◽  
Xufeng Liao ◽  
Zhangming Zhu ◽  
Yintang Yang
Keyword(s):  
High Precision ◽  
Maximum Output Power ◽  
Cmos Technology ◽  
Control Technique ◽  
Maximum Output ◽  
Active Rectifier ◽  
Offset Voltage ◽  
Piezoelectric Energy ◽  
Self Powered ◽  
Current Detection

In this paper, a power-enhanced active rectifier with high precision of current detection for piezoelectric energy harvesting (PEH) system is presented. A traditional two-stage active rectifier is adopted, which includes a first-stage negative voltage converter and an active diode. A comparator with offset control technique is proposed; thus the input-referred offset voltage of the proposed comparator can be less than 1[Formula: see text]mV. The current detected accuracy of the proposed offset-controlled comparator (OCC) is improved by more than 10 times over a traditional comparator. Output oscillations of the OCC are dramatically reduced attributing to the high precision of current detection. In addition, the OCC is also able to prevent the reverse leakage current. The design is implemented in an SMIC 0.18[Formula: see text][Formula: see text]m standard CMOS technology with a chip area of 0.22[Formula: see text]mm2. The measurement results show that the maximum output power, power conversion efficiency and figure of merit are 23.3[Formula: see text][Formula: see text]W, 90%, and 0.9, respectively, when the open-circuit voltage is 2.4[Formula: see text]V. The proposed rectifier can be self-powered without the additional external supply.

scholarly journals A CMOS Transmitter Analog Baseband for 5G Mobile Communication

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1319
Author(s):  
Yen ◽  
Chen ◽  
Wei ◽  
Chung
Keyword(s):  
Mobile Communication ◽  
Gain Control ◽  
Cmos Technology ◽  
Control Technique ◽  
Constant Current ◽  
Constant Current Density ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Analog Baseband ◽  
5G Mobile Communication

CMOS analog baseband circuits including a low-pass filter (LPF) and a programmable gain amplifier (PGA) are designed and implemented for the fifth-generation (5G) mobile communication. The super source follower topology is adopted to achieve a wideband LPF with good linearity, while the constant current density gain control technique is used to implement gain cells of the PGA. The circuits are integrated as an analog baseband for a 5G transmitter (TX) and fabricated using TSMC 90-nm CMOS technology. The analog baseband exhibits the bandwidth from 1.03 to 1.05 GHz when the voltage gain is varied from −18.9 dB to 3.8 dB in 1-dB steps. The gain step errors are within −0.7 dB to 0.9 dB. In the highest gain mode, the analog baseband achieves the IP1dB of −10 dBv and the IIP3 of −0.2 dBv. Over the band of interest, the NF of the analog baseband is 24.4–40.0 dB.

High Speed Analog Filters Using Scaled CMOS Technology

1999 ◽  
pp. 307-321
Author(s):  
R. Castello ◽  
I. Bietti ◽  
F. Svelto
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Analog Filters ◽  
Scaled Cmos
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