Low Phase Noise, 18kHz Frequency Tuning Step, 5GHz, 15bit Digitally Controlled Oscillator in 0.18µm CMOS Technology

2010 ◽  
Vol E93-C (7) ◽  
pp. 1007-1013
Author(s):  
Ramesh K. POKHAREL ◽  
Kenta UCHIDA ◽  
Abhishek TOMAR ◽  
Haruichi KANAYA ◽  
Keiji YOSHIDA
Keyword(s):  
Phase Noise ◽  
Frequency Tuning ◽  
Cmos Technology ◽  
Digitally Controlled ◽  
Digitally Controlled Oscillator ◽  
Low Phase Noise

A Wideband Gain Linearized Microwave Voltage Controlled Oscillator with Low Phase Noise Variation in Nanometer CMOS Technology

2015 ◽  
Vol 24 (03) ◽  
pp. 1550024 ◽  
Author(s):  
Mohammed Aqeeli ◽  
Abdullah Alburaikan ◽  
Cahyo Muvianto ◽  
Xianjun Huang ◽  
Zhirun Hu
Keyword(s):  
Phase Noise ◽  
Frequency Tuning ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Voltage Controlled Oscillator ◽  
Lower Phase ◽  
Nanometer Cmos ◽  
Digitally Controlled ◽  
Binary Weighted ◽  
Low Phase Noise

A wideband CMOS LC tank voltage-controlled oscillator (VCO) with low phase noise variations and a linearized gain has been designed using a new binary-weighted switched-capacitor and digitally-controlled varactor bank. The novel design has the advantages of more linear VCO frequency tuning, lower phase noise and reduced gain to variations in supply voltage. The proposed VCO has been designed using UMC 90-nm, 6-metal CMOS technology and features phase noise variation of less than 4.9 dBc/Hz. The VCO operates from 3.45 to 6.55 GHz, with phase noise of -133.4 dBc/Hz at a 1 MHz offset, a figure of merit (FoM) of -203.3 dBc/Hz, less than 41 dBm spurious harmonics, and a total VCO core current consumption of 1.18 mA from a 3.3 V voltage supply. To the authors' knowledge, this is the lowest phase noise variation ever reported.

scholarly journals Design of High Frequency, Low Phase Noise LC Digitally Controlled Oscillator for 5G Intelligent Transport Systems

Electronics ◽  
2019 ◽  
Vol 8 (1) ◽  
pp. 72 ◽  
Author(s):  
Vytautas Macaitis ◽  
Romualdas Navickas
Keyword(s):  
Phase Noise ◽  
Cmos Technology ◽  
Frequency Divider ◽  
Transport Systems ◽  
Intelligent Transport Systems ◽  
Intelligent Transport ◽  
Digitally Controlled ◽  
Digitally Controlled Oscillator ◽  
Offset Frequency ◽  
Low Phase Noise

This paper presents the design, simulation, and measurements of a low power, low phase noise 10.25–11.78 GHz LC digitally controlled oscillator (LC DCO) with extended true single phase clock (E-TSPC) frequency divider in 130 nm complementary metal–oxide–semiconductor (CMOS) technology for 5G intelligent transport systems. The main goal of this work was to design the LC DCO using a mature and low-cost 130 nm CMOS technology. The designed integrated circuit (IC) consisted of two parts: the LC DCO frequency generation and division circuit and an independent frequency divider testing circuit. The proposed LC DCO consisted of the following main blocks: the high Q-factor inductor, switched-capacitors block, cross-coupled transistors, and the current control block. Inductors with switched-capacitors block formed an LC tank. The designed E-TSPC frequency divider consisted of eight blocks connected in a series; each block increased the division ratio by a factor of two. The frequency of the input signal was divided in the region from two to 256 times using the designed divider. The main parameters of the designed E-TSPC divider and the LC DCO measurements were given as follows: LC DCO achieved a wide tuning range from 10.25 GHz to 11.78 GHz (1.53 GHz, 15.28% bandwidth); phase noise at 1 MHz offset frequency from LC DCO lowest carrier frequency was −113.42 dBc/Hz; phase noise at 1 MHz offset frequency from LC DCO highest carrier frequency was −110.51 dBc/Hz; The average power consumption of the designed LC DCO core and E-TSPC divider were 10.02 mW and 97.52 mW, respectively; the figure of merit (FOM) and the extended FOMT values of the proposed LC DCO were −183.52 dBc/Hz and −187.20 dBc/Hz, respectively. These FOM and FOMT results were achieved due to very low phase noise (−113.52 dBc/Hz) and a wide frequency tuning range (15.28%). The total layout area including the pads was 1.5 mm × 1.5 mm, with the largest part of the layout occupied by the proposed LC DCO (193 µm × 311 µm). The largest part of the LC DCO was occupied by the inductor 184 µm × 184 µm. The manufactured chip was packed into a quad flat no-leads (QFN) 20 pads package.

scholarly journals Optimum Layout of Low Power LC-Based Digitally Controlled Oscillator for Bluetooth Low Energy in a 4G/5G LTE System

2021 ◽  
Vol 11 (3) ◽  
pp. 1059
Author(s):  
Min-Su Kim ◽  
Sang-Sun Yoo
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Phase Noise ◽  
Supply Voltage ◽  
Low Energy ◽  
Superior Performance ◽  
Bluetooth Low Energy ◽  
Digitally Controlled ◽  
Digitally Controlled Oscillator ◽  
Low Phase Noise

This paper presents an optimum layout method of a low-power, digitally controlled oscillator (DCO) for a Bluetooth low-energy (BLE) transceiver in a 4G/5G LTE system. For the optimal LC-based DCO layout, three different layouts, including different gm cell locations and an Al metal layer, were implemented, and performance was compared and verified for BLE application. The implemented neck DCO (NDCO), where the gm cell is located in the neck of the main inductor, showed superior performance compared to other layouts in terms of low phase noise and low power consumption. The designed NDCO had a low phase noise of −116.1 dBc/Hz at 1 MHz with a 0.5 mW power consumption. The supply voltage and oscillation frequency range were 0.8 V and 4.7–5.7 GHz, respectively, and the NDCO designed with the optimal layout had a good figure-of-merit of −192.6 dBc/Hz.

A 5-mW, 1.2–3.5-GHz Capacitive Degeneration in LC-Digitally-Controlled Oscillator for Nano-Satellite Frequency Synthesizers in 90-nm CMOS

2016 ◽  
Vol 25 (12) ◽  
pp. 1650159 ◽  
Author(s):  
Sehmi Saad ◽  
Mongia Mhiri ◽  
Aymen Ben Hammadi ◽  
Kamel Besbes
Keyword(s):  
Phase Noise ◽  
Figure Of Merit ◽  
Frequency Synthesizers ◽  
Frequency Resolution ◽  
Lc Oscillator ◽  
Digitally Controlled ◽  
Additional Resistance ◽  
Capacitance Characteristics ◽  
Digitally Controlled Oscillator ◽  
Low Phase Noise

This paper proposes an 8-bit LC tuned digitally-controlled oscillator (DCO) that exploits a new tunable active inductor (TAI) with a high [Formula: see text]-factor. This TAI achieves a maximum [Formula: see text]-factor value of 98 over a frequency range of 1770[Formula: see text]MHz. It tunes from 3.55[Formula: see text]nH to 15.2[Formula: see text]nH. The proposed TAI is used in the resonator of a wide tunable low-phase-noise DCO-LC oscillator. The tuning circuitry of the DCO with an additional resistance contributes to better effective capacitance characteristics as compared to the basic topology. Thanks to the capacitive degeneration network formed by a resistance connected in parallel with a capacity, the achieved frequency resolution is between 3[Formula: see text]kHz and 16[Formula: see text]kHz without any dithering. The proposed DCO with capacitive degeneration oscillates at a frequency that can be tuned from 1.22 to 3.52[Formula: see text]GHz with 65% tuning range. It consumes 5.2-mA current from a 1.0-V voltage supply, achieves a phase noise of [Formula: see text]105.8[Formula: see text]dBc/Hz at 1-MHz offset and exhibits a figure of merit (FoM) of [Formula: see text]178[Formula: see text]dBc/Hz. The proposed digitally-controlled oscillator was implemented in TSMC 90-nm CMOS MS/RF technology.

A low-power and low-phase-noise LC digitally controlled oscillator featuring a novel capacitor bank

2010 ◽  
Vol 31 (12) ◽  
pp. 125003 ◽  
Author(s):  
Huanhuan Tian ◽  
Zhiqiang Li ◽  
Pufeng Chen ◽  
Rufei Wu ◽  
Haiying Zhang
Keyword(s):  
Low Power ◽  
Phase Noise ◽  
Capacitor Bank ◽  
Digitally Controlled ◽  
Digitally Controlled Oscillator ◽  
Low Phase Noise
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