scholarly journals A high-performance wear-leveling algorithm for flash memory system

2012 ◽  
Vol 9 (24) ◽  
pp. 1874-1880 ◽  
Author(s):  
Ching-Che Chung ◽  
Duo Sheng ◽  
Ning-Mi Hsueh
Keyword(s):  
Flash Memory ◽  
High Performance ◽  
Memory System ◽  
Wear Leveling

scholarly journals Improvement of Garbage Management for NAND Memory System

2018 ◽  
Vol 9 (3) ◽  
pp. 539
Author(s):  
A. Thileepan ◽  
S. Ramachandran
Keyword(s):  
Embedded Systems ◽  
Flash Memory ◽  
Memory Device ◽  
Memory System ◽  
Similar Technique ◽  
Wear Leveling ◽  
Set Up ◽  
Made In

<p>Recent days increasing the use of flash memory device in embedded systems. Diverse qualities of NAND blaze recollections from hard circles include: a constrained square eradicate check, the inconceivability of set up refresh, and asymmetry in operation granularity. Along these lines different rubbish accumulation procedures for the NAND streak recollections have been proposed. In any case, existing rubbish accumulation procedures obstruct square wear leveling since they utilize a similar technique for both hot and icy information. In this paper, we propose effective junk accumulation and piece administration strategies to enhance piece wear leveling and trash gathering speed. Above all else, information is arranged into three sorts concurring to alteration recurrence - hot information, cool information, and warm data and distinctive sorts of information are put away in various pieces. The delete cost is figured considering information sort, and afterward junk gathering is performed for the hinders whose eradicate costs surpass the limit esteem. Furthermore, unique square records are made in RAM by information sort, and the squares are orchestrated in the request of their eradicate cost.</p>

scholarly journals Design and Implementation of Smart Non-Invasive Bone Conduction Ear-Plug System

2018 ◽  
Vol 9 (2) ◽  
pp. 249
Author(s):  
Ravichandran G ◽  
M Krishnamurthy
Keyword(s):  
Low Power ◽  
Flash Memory ◽  
High Performance ◽  
Bone Conduction ◽  
Ultra Low Power ◽  
Audio Processing ◽  
Activity Tracker ◽  
Non Invasive ◽  
Run Up ◽  
Music Player

<p>The project aim is to design a smart earplug system integrated with non-invasive bone conduction technique which is capable of doing some advanced audio processing to provide voice enhancing, noise filtered audio for the hearing impaired people [2]. The system is also designed to work as an embedded music player, a life activity tracker and a Smartphone companion. It can even read the SMS that is just received on your smartphone into your ear. This project needs a very low power microcontroller but with high-performance signal processing requirements. STM32L476 from STMicroelectronics meets this needs and thus chosen as the main MCU. It is an ultra-low power ARM Cortex-M4 based microcontroller that can run up to 80MHz.  It has got 1MB of Flash memory and 128 KB RAM.</p>

scholarly journals A Block Classification Method with Monitor and Restriction in NAND Flash memory

2021 ◽  
Vol 12 (5) ◽  
pp. 209-215
Author(s):  
Myungsub Lee
Keyword(s):  
Performance Evaluation ◽  
Standard Deviation ◽  
Flash Memory ◽  
Garbage Collection ◽  
Memory Systems ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Wear Leveling ◽  
Block Classification ◽  
Update Frequency

In this paper, we propose a block classification with monitor and restriction (BCMR) method to isolate and reduce the interference of blocks in garbage collection and wear leveling. The proposed method monitors the endurance variation of blocks during garbage collection and detects hot blocks by making a restriction condition based on this information. This method induces block classification by its update frequency for garbage collection and wear leveling, resulting in a prolonged lifespan for NAND flash memory systems. The performance evaluation results show that the BCMR method prolonged the life of NAND flash memory systems by 3.95% and reduced the standard deviation per block by 7.4%, on average.

A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface

2012 ◽  
Vol 47 (4) ◽  
pp. 981-989 ◽  
Author(s):  
Chulbum Kim ◽  
Jinho Ryu ◽  
Taesung Lee ◽  
Hyunggon Kim ◽  
Jaewoo Lim ◽  
...  
Keyword(s):  
Flash Memory ◽  
High Performance ◽  
Nand Flash ◽  
Nand Flash Memory
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