scholarly journals Performance evaluation on high-speed multi-channel CWDM system by using offset-launch method and multi-stage decision feedback equalizer

2011 ◽  
Vol 8 (22) ◽  
pp. 1870-1875
Author(s):  
Fu-Hsiung Chen
Keyword(s):  
Performance Evaluation ◽  
High Speed ◽  
Decision Feedback ◽  
Decision Feedback Equalizer ◽  
Multi Stage

High Speed 1-tap Decision Feedback Equalizer in 28 nm CMOS

2014 ◽  
Vol 9 (9th) ◽  
pp. 1-12
Author(s):  
Mostafa Hosny ◽  
Sameh Ibrahim ◽  
DiaaEldin Khalil ◽  
Mohamed Dessouky
Keyword(s):  
High Speed ◽  
Decision Feedback ◽  
Decision Feedback Equalizer ◽  
28 Nm

scholarly journals A Low-Complexity Decision Feedforward Equalizer Architecture for High-Speed Receivers on Highly Dispersive Channels

2013 ◽  
Vol 2013 ◽  
pp. 1-10 ◽  
Author(s):  
Ariel L. Pola ◽  
Juan E. Cousseau ◽  
Oscar E. Agazzi ◽  
Mario R. Hueda
Keyword(s):  
Error Probability ◽  
High Speed ◽  
Low Complexity ◽  
Decision Feedback ◽  
Decision Feedback Equalizer ◽  
Channel Memory ◽  
Exponential Increase ◽  
Dispersive Channels ◽  
Large Memory ◽  
Feedforward Equalizer

This paper presents an improved decision feedforward equalizer (DFFE) for high speed receivers in the presence of highly dispersive channels. This decision-aided equalizer technique has been recently proposed for multigigabit communication receivers, where the use of parallel processing is mandatory. Well-known parallel architectures for the typical decision feedback equalizer (DFE) have a complexity that grows exponentially with the channel memory. Instead, the new DFFE avoids that exponential increase in complexity by using tentative decisions to cancel iteratively the intersymbol interference (ISI). Here, we demostrate that the DFFE not only allows to obtain a similar performance to the typical DFE but it also reduces the compelxity in channels with large memory. Additionally, we propose a theoretical approximation for the error probability in each iteration. In fact, when the number of iteration increases, the error probability in the DFFE tends to approach the DFE. These benefits make the DFFE an excellent choice for the next generation of high-speed receivers.

EQUALIZERS FOR HIGH-SPEED SERIAL LINKS

2005 ◽  
Vol 15 (02) ◽  
pp. 429-458 ◽  
Author(s):  
PAVAN KUMAR HANUMOLU ◽  
GU-YEON WEI ◽  
UN-KU MOON
Keyword(s):  
Continuous Time ◽  
High Speed ◽  
Decision Feedback ◽  
Decision Feedback Equalizer ◽  
Serial Links ◽  
Communication Links ◽  
Inter Symbol Interference

In this tutorial paper we present equalization techniques to mitigate inter-symbol interference (ISI) in high-speed communication links. Both transmit and receive equalizers are analyzed and high-speed circuits implementing them are presented. It is shown that a digital transmit equalizer is the simplest to design, while a continuous-time receive equalizer generally provides better performance. Decision feedback equalizer (DFE) is described and the loop latency problem is addressed. Finally, techniques to set the equalizer parameters adaptively are presented.

Sign in / Sign up

Export Citation Format

Share Document