scholarly journals Evaluating the performance of one-dimensional chaotic maps in the network-on-chip mapping problem

2009 ◽  
Vol 6 (12) ◽  
pp. 811-817 ◽  
Author(s):  
Golnar Gharooni-fard ◽  
Ahmad Khademzade ◽  
Fahime Moein-darbari
Keyword(s):  
Chaotic Maps ◽  
Network On Chip ◽  
Mapping Problem ◽  
One Dimensional ◽  
On Chip

scholarly journals CGMAP: a new approach to Network-on-Chip mapping problem

2009 ◽  
Vol 6 (1) ◽  
pp. 27-34 ◽  
Author(s):  
Fahime Moein-darbari ◽  
Ahmad Khademzade ◽  
Golnar Gharooni-fard
Keyword(s):  
Network On Chip ◽  
New Approach ◽  
Mapping Problem ◽  
On Chip

scholarly journals Applying Genetic Algorithm to Solve Partitioning and Mapping Problem for Mesh Network-on-Chip Systems

2021 ◽  
Vol 13 (1) ◽  
pp. 33-47
Author(s):  
Walid Mokthar Salh ◽  
Azeddien M. Sllame
Keyword(s):  
Genetic Algorithm ◽  
Power Consumption ◽  
Design Process ◽  
Network On Chip ◽  
Experimental Results ◽  
Mesh Network ◽  
Data Dependencies ◽  
Mapping Problem ◽  
Mesh Topology ◽  
On Chip

This paper presents a genetic based approach to the partitioning and mapping of multicore SoC cores over a NoC system that uses mesh topology. The proposed algorithm performs the partitioning and mapping by reducing communication cost and minimizing power consumption by placing those intercommunicated cores as close as possible together. A program developed in C++ in which the provided specification of the multicore MPSoC system captures all data dependencies before any start of the design process. Experimental results of several multimedia benchmarks demonstrates that the genetic-based approach able to find different satisfied implementations to the problem of partitioning and mapping of MPSoC cores over mesh-based NoC system that satisfies design goals.

Pre-allocated Path Based Low Latency Router Architecture for Network-on-chip

2014 ◽  
Vol 35 (2) ◽  
pp. 341-346
Author(s):  
Xiao-fu Zheng ◽  
Hua-xi Gu ◽  
Yin-tang Yang ◽  
Zhong-fan Huang
Keyword(s):  
Network On Chip ◽  
Low Latency ◽  
Router Architecture ◽  
On Chip
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