Design of low-power low-area asynchronous iterative multiplier

Heng You; Yong Hei; Jia Yuan; Weidi Tang; Xu Bai; Shushan Qiao

doi:10.1587/elex.16.20190212

Design of low-power low-area asynchronous iterative multiplier

IEICE Electronics Express ◽

10.1587/elex.16.20190212 ◽

2019 ◽

Vol 16 (11) ◽

pp. 20190212-20190212

Author(s):

Heng You ◽

Yong Hei ◽

Jia Yuan ◽

Weidi Tang ◽

Xu Bai ◽

...

Keyword(s):

Low Power ◽

Low Area

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A Low-Area and Low-Power Comma Detection and Word Alignment Circuits for JESD204B/C Controller

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2021.3072772 ◽

2021 ◽

pp. 1-11

Author(s):

Peng Yin ◽

Zhou Shu ◽

Yingjun Xia ◽

Tianmei Shen ◽

Xiao Guan ◽

...

Keyword(s):

Low Power ◽

Word Alignment ◽

Low Area

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Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core

9th EUROMICRO Conference on Digital System Design (DSD'06) ◽

10.1109/dsd.2006.40 ◽

2006 ◽

Cited By ~ 140

Author(s):

P. Hamalainen ◽

T. Alho ◽

M. Hannikainen ◽

T.D. Hamalainen

Keyword(s):

Low Power ◽

Low Area ◽

Design And Implementation

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A novel low power, low area array multiplier design for DSP applications

2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies ◽

10.1109/icsccn.2011.6024554 ◽

2011 ◽

Cited By ~ 3

Author(s):

N. Ravi ◽

Y. Subbaiah ◽

T.Jayachandra Prasad ◽

T.Subba Rao

Keyword(s):

Low Power ◽

Low Area ◽

Area Array ◽

Array Multiplier ◽

Dsp Applications

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Hardware Implementation of Low-Power Low-Area Programmable Interval Type-2 Fuzzifier

Electrical Engineering (ICEE), Iranian Conference on ◽

10.1109/icee.2018.8472446 ◽

2018 ◽

Author(s):

Rouhollah Mohammadi Nasr ◽

Abdollah Khoei

Keyword(s):

Low Power ◽

Hardware Implementation ◽

Low Area ◽

Interval Type

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A low power low area crosstalk avoidance logic for 45nm ASIC applications

2017 International Conference on Intelligent Computing and Control (I2C2) ◽

10.1109/i2c2.2017.8321826 ◽

2017 ◽

Author(s):

P. Sudhakara Rao ◽

Battari Obulesu

Keyword(s):

Low Power ◽

Low Area ◽

Crosstalk Avoidance

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Low-Power, Low-Area Multi-level 2-D Discrete Wavelet Transform Architecture

Circuits Systems and Signal Processing ◽

10.1007/s00034-017-0553-2 ◽

2017 ◽

Vol 37 (1) ◽

pp. 444-458 ◽

Cited By ~ 5

Author(s):

Saad Al-Azawi

Keyword(s):

Wavelet Transform ◽

Low Power ◽

Discrete Wavelet Transform ◽

Discrete Wavelet ◽

Low Area ◽

Multi Level ◽

Level 2

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Low Power Low Area Implementation of CORDIC Architecture Using Carry Select Adder for Realtime DSP Applications

2020 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT) ◽

10.1109/conecct50063.2020.9198608 ◽

2020 ◽

Author(s):

Lakshmi Shrinivasan ◽

Krishika Ponnamma C.R.

Keyword(s):

Low Power ◽

Low Area ◽

Carry Select Adder ◽

Dsp Applications

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The low-power and low-area PWM by light intensity for photoflash in 0.35-μm CMOS

2008 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2008.4541770 ◽

2008 ◽

Author(s):

Woo Kwan Lee ◽

Won Ho Choi ◽

Young Jae Min ◽

Hoon Ki Kim ◽

Soo-Won Kim

Keyword(s):

Light Intensity ◽

Low Power ◽

Low Area

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A low power low area capacitor array based Digital to Analog Converter architecture

Microelectronics Journal ◽

10.1016/j.mejo.2015.07.010 ◽

2015 ◽

Vol 46 (10) ◽

pp. 928-934 ◽

Cited By ~ 3

Author(s):

A. Purushothaman ◽

Chetan D. Parikh

Keyword(s):

Low Power ◽

Digital To Analog Converter ◽

Low Area ◽

Capacitor Array ◽

Analog Converter ◽

Digital To Analog

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Optimum primitive polynomials for low-area low-power finite field semi-systolic multipliers

1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing ◽

10.1109/sips.1997.626273 ◽

2002 ◽

Cited By ~ 2

Author(s):

L. Song ◽

K.K. Parhi

Keyword(s):

Finite Field ◽

Low Power ◽

Low Area ◽

Primitive Polynomials

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