scholarly journals Low-overhead, one-cycle timing-error detection and correction technique for flip-flop based pipelines

2019 ◽  
Vol 16 (11) ◽  
pp. 20190180-20190180
Author(s):  
Jongeun Koo ◽  
Eunhyeok Park ◽  
Dongyoung Kim ◽  
Junki Park ◽  
Sungju Ryu ◽  
...  
Keyword(s):  
Error Detection ◽  
Timing Error ◽  
Flip Flop ◽  
Correction Technique ◽  
Error Detection And Correction

scholarly journals A One-Cycle Correction Error-Resilient Flip-Flop for Variation-Tolerant Designs on an FPGA

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 633
Author(s):  
Dam Minh Tung ◽  
Nguyen Van Toan ◽  
Jeong-Gun Lee
Keyword(s):  
Integrated Circuits ◽  
Error Detection ◽  
Error Resilience ◽  
Cycle Performance ◽  
Timing Error ◽  
Worst Case ◽  
Flip Flop ◽  
Error Detection And Correction ◽  
Field Programmable ◽  
Performance Penalty

Timing error resilience (TER) is one of the most promising approaches for eliminating design margins that are required due to process, voltage, and temperature (PVT) variations. However, traditional TER circuits have been designed typically on an application-specific integrated circuits (ASIC) where customized circuits and metastability detector designs at a transistor level are possible. On the other hand, it is difficult to implement those designs on a field-programmable gate array (FPGA) due to its predefined LUT structure and irregular wiring. In this paper, we propose an error detection and correction flip-flop (EDACFF) on an FPGA chip, where the metastability issue can be resolved by imposing proper timing constraints on the circuit structures. The proposed EDACFF exploits a transition detector for detecting a timing error along with a data correction latch for correcting the error with one-cycle performance penalty. Our proposed EDACFF is implemented in a 3-bit counter circuit employing a 5-stage pipeline on a Spartan-6 FPGA device (the XFC6SLX45) to verify the functional and timing behavior. The measurement results show that the proposed design obtains 32% less power consumption and 42% higher performance compared to a traditional worst-case design.

Offset DMR: A Low Overhead Soft Error Detection and Correction Technique for Transform-Based Convolution

2011 ◽  
Vol 60 (10) ◽  
pp. 1511-1516 ◽  
Author(s):  
Pedro Reviriego ◽  
Chris Bleakley ◽  
Juan Antonio Maestro ◽  
Anne O'Donnell
Keyword(s):  
Error Detection ◽  
Soft Error ◽  
Correction Technique ◽  
Error Detection And Correction

scholarly journals SEC-TAED based Error Detection and Correction Technique for Data Transmission Systems

2018 ◽  
Vol 10 (2) ◽  
pp. 696
Author(s):  
Mr. G. Manikandan ◽  
Dr. M. Anand
Keyword(s):  
Error Detection ◽  
Gaussian Noise ◽  
Data Transmission ◽  
High Speed ◽  
Additive White Gaussian Noise ◽  
Hamming Code ◽  
Correction Technique ◽  
Error Detection And Correction ◽  
Placement Algorithm ◽  
Original Information

<p>In the OFDM communication system channel encoder and decoder is the part of the architecture. OFDM channel is mostly affected by Additive White Gaussian Noise (AWGN) in which bit flipping of original information leads to fault transmission in the channel. To overcome this problem by using hamming code for error detection and correction. Hamming codes are more attractive and it easy to process the encoding and decoding with low latency. In general the hamming is perfectly detected and corrects the single bit error. In this paper, design of single Error Correction-Triple Adjacent Error Detection (SEC-TAED) codes with bit placement algorithm is presented with less number of parity bits. In the conventional Double Adjacent Error Detection (DAED) and Hamming (13, 8) SEC-TAED are process the codes and detects the error, but it require more parity bits for performing the operation. The higher number of parity bits causes processing delay. To avoid this problem by proposed the Hamming (12, 8) SEC-TAED code, it require only four parity bits to perform the detection process. Bit-reordered format used in the method increases the probability detection of triple adjacent error. It is more suitable for efficient and high speed communication.</p>

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