Future Directions of Non-volatile Memory Technologies

2004 ◽  
Vol 830 ◽  
Author(s):  
Albert Fazio
Keyword(s):  
Flash Memory ◽  
Low Cost ◽  
Memory Cell ◽  
Current Status ◽  
Technology Scaling ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
Complex Structural ◽  
Flash Memory Cell ◽  
To Come

ABSTRACTIt expected that for many years to come, the majority of the nonvolatile memories shipped will be based on current mainstream flash technologies, which utilize transistor based charge storage memory cells and multi-level-cell concepts, for storing more than one logic bit in a single physical cell. Moore's law will continue to drive transistor based memory technology scaling but technology complexity will be increasing. In order to meet technology scaling, the mainstream transistor based flash technologies will start evolving to incorporate material and structural innovations. This paper will review the current status and discuss the approaches being explored to provide scaling solutions for future transistor based non-volatile memory products. Based on the introduction of material innovations, it is expected that the planar transistor based flash memory cell can scale into the 32nm node. Further, more complex, structural innovations will be required to maintain further scaling. New memory concepts, not relying on transistors as a basis of the memory cell, provide new opportunities for future low cost memories. Several of these new concepts will be summarized and contrasted with the mainstream transistor based flash memory technologies.

Flash Memory Scaling

MRS Bulletin ◽  
2004 ◽  
Vol 29 (11) ◽  
pp. 814-817 ◽  
Author(s):  
Al Fazio
Keyword(s):  
Data Storage ◽  
Flash Memory ◽  
Nonvolatile Memory ◽  
Three Dimensional ◽  
Memory Cell ◽  
Current Status ◽  
Memory Cells ◽  
Technology Scaling ◽  
Complex Structural ◽  
High Dielectric

AbstractIn order to meet technology scaling in the field of solid-state memory and data storage, the mainstream transistor-based flash technologies will start evolving to incorporate material and structural innovations. Dielectric scaling in nonvolatile memories is approaching the point where new approaches will be required to meet the scaling requirements while simultaneously meeting the reliability and performance requirements of future products. High-dielectric-constant materials are being explored as possible candidates to replace the traditional SiO2 and ONO (oxide/nitride/oxide) films used today in memory cells. Likewise, planar-based memory cell scaling is approaching the point where scaling constraints force exploration of new materials and nonplanar, three-dimensional scaling alternatives. This article will review the current status and discuss the approaches being explored to provide scaling solutions for future transistor floating-gate-based nonvolatile memory products. Based on the introduction of material innovations, it is expected that the planar transistor-based flash memory cells can scale through at least the end of the decade (2010) using techniques that are available today or projected to be available in the near future. More complex, structural innovations will be required to achieve further scaling.

The Flash Memory Cell for the Nodes to Come: Material Requirements from a Device Perspective

2019 ◽  
Vol 19 (2) ◽  
pp. 649-668 ◽  
Author(s):  
Bogdan Govoreanu ◽  
Jorge A. Kittl ◽  
Joeri De Vos ◽  
Aude Rothschild ◽  
Pieter Blomme ◽  
...  
Keyword(s):  
Flash Memory ◽  
Memory Cell ◽  
Flash Memory Cell ◽  
To Come ◽  
Material Requirements

Carrier Profiling of the 10-nm-order Structure in a 3D Flash Memory Cell Using Scanning Nonlinear Dielectric Microscopy

2019 ◽  
Author(s):  
Jun Hirota ◽  
Ken Hoshino ◽  
Tsukasa Nakai ◽  
Kohei Yamasue ◽  
Yasuo Cho
Keyword(s):  
Spatial Resolution ◽  
Flash Memory ◽  
Analytical Techniques ◽  
Memory Cell ◽  
Memory Device ◽  
Floating Gate ◽  
Order Structure ◽  
Carrier Distribution ◽  
Nonlinear Dielectric ◽  
Flash Memory Cell

Abstract In this paper, the authors report their successful attempt to acquire the scanning nonlinear dielectric microscopy (SNDM) signals around the floating gate and channel structures of the 3D Flash memory device, utilizing the custom-built SNDM tool with a super-sharp diamond tip. The report includes details of the SNDM measurement and process involved in sample preparation. With the super-sharp diamond tips with radius of less than 5 nm to achieve the supreme spatial resolution, the authors successfully obtained the SNDM signals of floating gate in high contrast to the background in the selected areas. They deduced the minimum spatial resolution and seized a clear evidence that the diffusion length differences of the n-type impurity among the channels are less than 21 nm. Thus, they concluded that SNDM is one of the most powerful analytical techniques to evaluate the carrier distribution in the superfine three dimensionally structured memory devices.

Quantum Dot Gate (QDG) Quantum Dot Channel (QDC) Multistate Logic Non-Volatile Memory (NVM) with High-K Dielectric HfO2 Barriers

2020 ◽  
Vol 29 (01n04) ◽  
pp. 2040001
Author(s):  
N. R. Butterfield ◽  
R. Mays ◽  
B. Khan ◽  
R. Gudlavalleti ◽  
F. C. Jain
Keyword(s):  
Quantum Dot ◽  
Hafnium Oxide ◽  
Experimental Testing ◽  
Memory Cell ◽  
Floating Gate ◽  
Carrier Injection ◽  
High K ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
High K Dielectric

This paper presents the theory, fabrication and experimental testing results for a multiple state Non-Volatile Memory (NVM), comprised of hafnium oxide high-k dielectric tunnel and gate barriers as well as a Silicon Quantum Dot Superlattice (QDSL) implemented for the floating gate and inversion channel (QDG) and (QDC) respectively. With the conclusion of Moore’s Law for conventional transistor fabrication, regarding the minimum gate size, current efforts in memory cell research and development are focused on bridging the gap between the conventions of the past sixty years and the future of computing. One method of continuing the increasing chip density is to create multistate devices capable of storing and processing additional logic states beyond 1 and 0. Replacing the silicon nitride floating gate of a conventional Flash NVM with QDSL gives rise to minibands that result in greater control over charge levels stored in the QDG and additional intermediate states. Utilizing Hot Carrier Injection (HCI) programming, for the realized device, various magnitudes of gate voltage pulses demonstrated the ability to accurately control the charge levels stored in the QDG. This corresponds to multiple threshold voltage shifts allowing detection of multiple states during read operations.

Flash Memory Cell Compact Modeling Using PSP Model

2008 ◽  
Author(s):  
Anthony Maure ◽  
Pierre Canet ◽  
Frederic Lalande ◽  
Bertrand Delsuc ◽  
Jean Devin
Keyword(s):  
Flash Memory ◽  
Memory Cell ◽  
Compact Modeling ◽  
Flash Memory Cell
Sign in / Sign up

Export Citation Format

Share Document