Self-Assembly CoSi2-Nanostructures for Fabrication of Schottky Barrier MOSFETs on SOI

2001 ◽  
Vol 686 ◽  
Author(s):  
Patrick Kluth ◽  
Qing-Tai Zhao ◽  
Stephan Winnerl ◽  
Siegfried Mantl

AbstractA new self-assembly patterning method for generation of epitaxial CoSi2 nanostructures was used to fabricate 70 nm gate-length Schottky barrier metal oxide semiconductor field effect transistors (SBMOSFETs) on silicon-on-insulator (SOI) substrates. This technique involves only conventional optical lithography and standard silicon processing steps. It is based on anisotropic diffusion of Co/Si atoms in a strain field during rapid thermal processing. The strain field is generated along the edges of a mask consisting of 20 nm SiO2 and 300 nm Si3N4. Single-crystalline CoSi2 layers grown by molecular beam allotaxy (MBA) on thin SOI substrates were patterned using this technique. During rapid thermal oxinitridation (RTON) of the masked silicide structure, a well defined separation of the silicide layer forms along the edge of the mask. These highly uniform gaps define the channel region of the fabricated device. The separated silicide layers act as metal source and drain. During the RTON-step a 6 nm thin SiO2 is formed on top of the gap which is used as a gate oxide. The SBMOSFETs can be driven as both p-channel and n-channel devices without complementary substrate doping and show good I-V characteristics.

2004 ◽  
Vol 810 ◽  
Author(s):  
Moongyu Jang ◽  
Yarkyeon Kim ◽  
Jaeheon Shin ◽  
Kyoungwan Park ◽  
Seongjae Lee

ABSTRACTThe stable growth conditions of erbium-silicide on silicon-on-insulator (SOI) are investigated considering annealing temperature, SOI and sputtered erbium thickness. From the sheet resistance measurement, X-ray diffraction and Auger electron spectroscopy analysis, the optimum annealing temperature is determined as 500°C. Also, for the stable growth of erbium- silicide on SOI, the sputtered erbium thickness should be less than 1.5 times of SOI thickness. As the SOI thickness decreases below this critical thickness, erbium-rich region is formed at the erbium-silicide and buried-oxide interface. By applying the optimized erbium-silicide growth conditions, 50-nm-gate-length n-type SB-MOSFET is manufactured, which shows the possible usage of erbium-silicide as the source and drain material in the n-type Schottky barrier MOSFETs for decananometer regime applications.


2006 ◽  
Vol 913 ◽  
Author(s):  
Joachim Knoch ◽  
Min Zhang ◽  
Qing-Tai Zhao ◽  
Siegfried Mantl

AbstractIn this paper we demonstrate the use of dopant segregation during silicidation for decreasing the effective potential barrier height in Schottky-barrier metal-oxide-semiconductor field-effect-transistors (SB-MOSFETs). N-type as well as p-type devices are fabricated with arsenic/boron implanted into the device's source and drain regions prior to silicidation. During full nickel silicidation a highly doped interface layer is created due to dopants segregating at the silicide-silicon interface. This doped layer leads to an increased tunneling probability through the Schottky barrier and hence leads to significantly improved device characteristics. In addition, we show with simulations that employing ultrathin body (UTB) silicon-on-insulator and ultrathin gate oxides allows to further improve the device characteristics.


2008 ◽  
Vol 44 (2) ◽  
pp. 159 ◽  
Author(s):  
C.-J. Choi ◽  
M.-G. Jang ◽  
Y.-Y. Kim ◽  
M.-S. Jun ◽  
T.-Y. Kim ◽  
...  

Author(s):  
N. David Theodore ◽  
Andre Vantomme ◽  
Peter Crazier

Contact is typically made to source/drain regions of metal-oxide-semiconductor field-effect transistors (MOSFETs) by use of TiSi2 or CoSi2 layers followed by AI(Cu) metal lines. A silicide layer is used to reduce contact resistance. TiSi2 or CoSi2 are chosen for the contact layer because these silicides have low resistivities (~12-15 μΩ-cm for TiSi2 in the C54 phase, and ~10-15 μΩ-cm for CoSi2). CoSi2 has other desirable properties, such as being thermally stable up to >1000°C for surface layers and >1100°C for buried layers, and having a small lattice mismatch with silicon, -1.2% at room temperature. During CoSi2 growth, Co is the diffusing species. Electrode shorts and voids which can arise if Si is the diffusing species are therefore avoided. However, problems can arise due to silicide-Si interface roughness (leading to nonuniformity in film resistance) and thermal instability of the resistance upon further high temperature annealing. These problems can be avoided if the CoSi2 can be grown epitaxially on silicon.


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