Single Crystal Gd203 Films Epitaxially Grown on GaAs - A New Dielectric for GaAs Passivation

1998 ◽  
Vol 535 ◽  
Author(s):  
M. Hong ◽  
J. Kwo ◽  
A. R. Kortan ◽  
J. P. Mannaerts ◽  
M. C. Wu ◽  
...  
Keyword(s):  
Oxide Film ◽  
Single Crystal ◽  
Oxide Semiconductor ◽  
Breakdown Field ◽  
Zero Bias ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Capacitance Voltage ◽  
Current Densities ◽  
And Inversion

AbstractSingle crystal Gd2O3 dielectric thin films were epitaxially grown on GaAs. The Gd2O3 film has a cubic structure isomorphic to Mn2O3, and is (110) oriented in single domain on the (100) GaAs surface. The oxide film has low leakage current densities ˜ 10–9 – 10–10 A/cmT2 at zero bias. Typical breakdown field is 4 MV/cm for an oxide film 185 Å thick, and >10 MV/cm for an oxide less than 50 Å thick. Both accumulation and inversion layers were observed in the Gd2O3-GaAs metal oxide semiconductor (MOS) diodes using capacitance-voltage (C-V) measurements, with an interfacial density of states around 1011 cm–2 eV–1.

A Study of Pt/AlN/6H-SiC MIS Structures for Device Applications

2000 ◽  
Vol 622 ◽  
Author(s):  
Margarita P. Thompson ◽  
Gregory W. Auner ◽  
Changhe Huang ◽  
James N. Hilfiker
Keyword(s):  
Plasma Source ◽  
Film Structure ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Current Voltage ◽  
Aln Film ◽  
Capacitance Voltage ◽  
Device Applications ◽  
Current Densities ◽  
Mis Structures

ABSTRACTAlN films with thicknesses from 53 to 79 nm were deposited on 6H-SiC substrates via Plasma Source Molecular Beam Epitaxy (PSMBE). The influence of deposition temperature on the growth mode and film roughness was assessed. The optical constants of the films in the range 0.73-8.75 eV were determined using spectroscopic ellipsometry. Pt/AlN/6H-SiC MIS structures were created and current-voltage (I-V) and capacitance-voltage (C-V) measurements were performed at room temperature and at 250°C. Most of the MIS structures showed rectifying I-V characteristics regardless of growth temperature. A 120-nm-thick AlN film was deposited at 500°C. MIS structures created on this film showed a very low leakage current densities of 6×10−8 A/cm2. The dielectric constant of the film was estimated at approximately 9. The relation between film structure and electrical properties of the films is discussed.

scholarly journals Effect of catalyst HF concentration on the electrical characteristics of ultra low-k materials

2012 ◽  
Vol 6 (2) ◽  
pp. 97-101 ◽  
Author(s):  
Zhi-Wei He ◽  
Shi-Qiu Zhu ◽  
Sheng-Li Wang ◽  
Zheng Qi ◽  
Yu-Yuan Guan
Keyword(s):  
Dielectric Constant ◽  
Sol Gel ◽  
Breakdown Field ◽  
Moisture Resistance ◽  
Electrical Characteristics ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Sol Gel Process ◽  
Capacitance Voltage ◽  
Low K

The effects of catalyst HF concentration on the dielectric and electrical properties of SiOF films are discussed. From the current density-voltage and capacitance-voltage curves, we observed that the film catalyzed with the special concentration of HF (the ratio of HF/H2O = 1/5) shows good moisture resistance, low leakage current (10-11 A/cm2 at 1 MV/cm) and high breakdown field (6 MV/cm), which can be explained by the results of Fourier transform infrared spectra. The dielectric constant value is also very low and reaches about 1.75 after annealing at the temperature of 450?C. Therefore, the concentration of HF catalyst is an important factor in the sol-gel process.

scholarly journals Гетеробарьерные варакторы с неоднородно легированными модулирующими слоями

2019 ◽  
Vol 45 (20) ◽  
pp. 51
Author(s):  
Н.А. Малеев ◽  
М.А. Бобров ◽  
А.Г. Кузьменков ◽  
А.П. Васильев ◽  
М.М. Кулагина ◽  
...  
Keyword(s):  
Numerical Model ◽  
Leakage Current ◽  
Molecular Beam ◽  
Voltage Characteristic ◽  
Doping Profile ◽  
Published Data ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Inp Substrate ◽  
Capacitance Voltage

Optimal capacitance-voltage characteristic is critical for heterobarrier varactor diode (HBV) performance in terms of multiplication efficiency in mm- and sub-mm wave ranges. Numerical model of capacitance-voltage characteristics and leakage current for HBV with arbitrary heterostructure composition and doping profile was verified on published data and original experimental results. Designed HBV heterostructure with three undoped InAlAs/AlAs/InAlAs barriers surrounded with non-uniformly doped n-InGaAs modulation layers was grown by molecular-beam epitaxy on InP substrate and test HBV diodes have been fabricated. Test HBV diodes demonstrate capacitance-voltage characteristics with cosine shape at bias voltage up to two volts, increased capacitance ratio and low leakage current values.

scholarly journals Characterization of Electrical Traps Formed in Al2O3 under Various ALD Conditions

Materials ◽  
2020 ◽  
Vol 13 (24) ◽  
pp. 5809
Author(s):  
Md. Mamunur Rahman ◽  
Ki-Yong Shin ◽  
Tae-Woo Kim
Keyword(s):  
Leakage Current ◽  
Deposition Temperature ◽  
Fundamental Property ◽  
Frequency Dispersion ◽  
Atomic Layer ◽  
Oxide Semiconductor ◽  
Semiconductor Interface ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Deposited Film

Frequency dispersion in the accumulation region seen in multifrequency capacitance–voltage characterization, which is believed to be caused mainly by border traps, is a concerning issue in present-day devices. Because these traps are a fundamental property of oxides, their formation is expected to be affected to some extent by the parameters of oxide growth caused by atomic layer deposition (ALD). In this study, the effects of variation in two ALD conditions, deposition temperature and purge time, on the formation of near-interfacial oxide traps in the Al2O3 dielectric are examined. In addition to the evaluation of these border traps, the most commonly examined electrical traps—i.e., interface traps—are also investigated along with the hysteresis, permittivity, reliability, and leakage current. The results reveal that a higher deposition temperature helps to minimize the formation of border traps and suppress leakage current but adversely affects the oxide/semiconductor interface and the permittivity of the deposited film. In contrast, a longer purge time provides a high-quality atomic-layer-deposited film which has fewer electrical traps and reasonable values of permittivity and breakdown voltage. These findings indicate that a moderate ALD temperature along with a sufficiently long purge time will provide an oxide film with fewer electrical traps, a reasonable permittivity, and a low leakage current.

Influence of Diverse Post-Trench Processes on the Electrical Performance of 4H-SiC MOS Structures

2014 ◽  
Vol 778-780 ◽  
pp. 595-598 ◽  
Author(s):  
Christian T. Banzhaf ◽  
Michael Grieb ◽  
Achim Trautmann ◽  
Anton J. Bauer ◽  
Lothar Frey
Keyword(s):  
Dielectric Breakdown ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Electrical Performance ◽  
Breakdown Field ◽  
Static Capacitance ◽  
Capacitance Voltage ◽  
Oxide Deposition ◽  
Mos Structures ◽  
Field Strengths

This paper focuses on the evaluation of subsequent process steps (post-trench processes, PTPs) after 4H silicon carbide (4H-SiC) trench etching with respect to the electrical performance of trenched gate metal oxide semiconductor field effect transistors (Trench-MOSFETs). Two different types of PTP were applied after 4H-SiC trench formation, a high temperature post-trench anneal (PTA) [1] and a sacrificial oxidation (SacOx) [2]. We found significantly improved electrical properties of Planar-MOS structures using a SacOx as PTP, prior to gate oxide deposition. Besides excellent quasi-static capacitance-voltage (QSCV) behavior even at T = 250 °C, charge-to-breakdown (QBD) results up to 8.8 C/cm2 at T = 200 °C are shown to be similar on trenched surfaces as well as on untrenched surfaces of SacOx-treated Planar-MOS structures. Moreover, dielectric breakdown field strengths up to 12 MV/cm have been measured on Planar-MOS structures. However, thick bottom oxide Trench-MOS structures indicate best dielectric breakdown field strengths of 9.5 MV/cm when using a trench shape rounding PTA as the PTP.

scholarly journals Very High Sustainable Forward Current Densities on 4H-SiC p-n Junctions Formed by VLS Localized Epitaxy of Heavily Al-Doped p++ Emitters

2017 ◽  
Vol 897 ◽  
pp. 63-66
Author(s):  
Selsabil Sejil ◽  
Loic Lalouat ◽  
Mihai Lazar ◽  
Davy Carole ◽  
Christian Brylinski ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Electrical Measurements ◽  
Pin Diodes ◽  
Low Leakage ◽  
Forward Current ◽  
Low Leakage Current ◽  
Current Densities ◽  
P Type ◽  
Electrical Characterizations ◽  
Very High

This study deals with the electrical characterization of PiN diodes fabricated on a 4°off-axis 4H-SiC n+ substrate with a n- epilayer (1×1016 cm-3 / 10 µm). Optimized p++ epitaxial areas were grown by Vapour-Liquid-Solid (VLS) transport to form p+ emitters localized in etched wells with 1 µm depth. Incorporated Al level in the VLS p++ zones was checked by SIMS (Secondary Ion Mass Spectroscopy), and the doping level was found in the range of 1-3×1020 at.cm-3. Electrical characterizations were performed on these PiN diodes, with 800 nm deposit of aluminium as ohmic contact on p-type SiC. Electrical measurements show a bipolar behaviour, and very high sustainable forward current densities ≥ 3 kA.cm-2, preserving a low leakage current density in reverse bias. These measurements were obtained on structures without any passivation and no edge termination.

Low-voltage field emission from tungsten fiber arrays in a stabilized zirconia matrix

1987 ◽  
Vol 2 (3) ◽  
pp. 322-328 ◽  
Author(s):  
J. K. Cochran ◽  
A. T. Chapman ◽  
D. N. Hill ◽  
K. J. Lee
Keyword(s):  
Low Voltage ◽  
Circular Cylinders ◽  
High Resistivity ◽  
Stabilized Zirconia ◽  
Fiber Arrays ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Emission Testing ◽  
Current Densities ◽  
Field Emitter Array

Field emitter array cathodes were fabricated from unidirectionally solidified composites of tungsten fibers in an insulating yttria-stabilized-zirconia (YSZ) matrix. A close-spaced molybdenum gate film (extractor) was formed utilizing c-beam evaporation of alumina as an insulator, which was overlayed by the molybdenum extractor. The high resistivity of the composite matrix coupled with the alumina insulator resulted in low leakage current and permitted dc operation of the device. Emission testing demonstrated current densities of 1–5 A/cm2 with leakage in the μA range for applied potentials of 125–200 V. Variation of emitter tip geometries from hemispheres to right circular cylinders to pointed cones produced increases in emission consistent with reduced tip radii.

Capacitance-Voltage Characterization of Pulsed Plasma Polymerized Allylamine Dielectrics

2002 ◽  
Vol 736 ◽  
Author(s):  
Yifan Xu ◽  
Paul Berger ◽  
Jai Cho ◽  
Richard B. Timmons
Keyword(s):  
Heat Treatment ◽  
Dielectric Constant ◽  
Film Deposition ◽  
Pulsed Plasma ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Heat Treated ◽  
Capacitance Voltage ◽  
Mobile Ions

ABSTRACTPolyallylamine films, deposited on Si wafers by radio frequency (RF) pulsed plasma polymerization (PPP), were employed as insulating layers of metal-insulator-semiconductor (MIS) capacitors. The insulating polymer films were deposited at substrate temperatures of 25°C and 100°C. Multiple frequency capacitance-voltage (C-V) measurements indicated that an in-situ heat treatment during film deposition increased the insulator dielectric constant. The dielectric constant, calculated from the C-V data, rose from 3.03 for samples with no heat treatment to 3.55 for samples with an in-situ heat treatment. For both sample sets, the I-V data demonstrate a low leakage current value (<20fA) up to 100V with an area of 0.0307 mm2, resulting in a current density of <0.65 pA/mm2. Hysteresis in the C-V curves with differing sweep directions was more pronounced for in-situ heat-treated samples indicative of positive mobile ions.

Methods to Improve Properties of Gate Dielectrics in Metal-Oxide-Semiconductor

2012 ◽  
Vol 463-464 ◽  
pp. 1341-1345 ◽  
Author(s):  
Chong Liu ◽  
Xiao Li Fan
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Dielectric Materials ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Physical Limitation ◽  
Low Leakage ◽  
Mos Devices ◽  
Low Leakage Current ◽  
High K

This essay aims to introduce development of gate dielectrics. In present-day society, Si-based MOS has met its physical limitation. Scientists are trying to find a better material to reduce the thickness and dimension of MOS devices. While substrate materials are required to have a higher mobility, gate dielectrics are expected to have high k, low Dit and low leakage current. I conclude dielectrics in both Si-based and Ge-based MOS devices and several measures to improve the properties of these gate dielectric materials. I also introduce studies on process in our group and some achievements we have got. Significantly, this essay points out the special interest in rare-earth oxides functioning as gate dielectrics in recent years and summarizes the advantages and problems should be resolved in future.

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