Analysis of Stresses and Strains In Passivated Metal Lines

1996 ◽  
Vol 436 ◽  
Author(s):  
I. Eppler ◽  
H. Schroeder ◽  
U. Burges ◽  
W. Schilling
Keyword(s):  
Integrated Circuits ◽  
Shear Deformation ◽  
Plastic Shear ◽  
Thermally Induced ◽  
Flat Substrate ◽  
Thermal Expansion Coefficients ◽  
Aspect Ratios ◽  
Induced Stresses ◽  
Proper Values ◽  
Passivated Metal

AbstractPassivated metal lines, commonly used in integrated circuits, show thermally induced stresses due to the difference of the thermal expansion coefficients of the lines and their surroundings. These stresses cause voidage and plastic flow of the lines. Aim of the analysis was to derive equations connecting experimentally measured strains or stresses by the X-ray diffraction and wafer curvature techniques with the magnitude of voidage and plastic shear deformation of the lines.Using the concepts of linear elasticity the volume averaged stresses of an array of parallel interconnects embedded in a passivation layer on a flat substrate are analysed. Equations are derived connecting the volume averaged stresses in the metal and in the passivation with the “Heigen-strains” of the metal which characterize the true (stress free) thermal strains and plastic deformation strains of the metal. The coefficients entering these equations are determined from (elastic) finite element method (FEM) calculations performed for various geometries and aspect ratios of the metal lines. Choosing the proper values of the coefficients allows the eigen- strains to be determined from the experimental data.By comparison of the evaluated eigen-strains with the purely elastic eigen-strains ΔαΔT the extent of voidage and/or plastic shear deformation of passivated metal lines caused by thermally induced stresses can be determined model independently.

Analysis Of Stresses And Strains In Passivated Metal Lines

1996 ◽  
Vol 428 ◽  
Author(s):  
I. Eppler ◽  
H. Schroeder ◽  
U. Burges ◽  
W. Schilling
Keyword(s):  
Integrated Circuits ◽  
Shear Deformation ◽  
Plastic Shear ◽  
Thermally Induced ◽  
Flat Substrate ◽  
Thermal Expansion Coefficients ◽  
Aspect Ratios ◽  
Induced Stresses ◽  
Proper Values ◽  
Passivated Metal

AbstractPassivated metal lines, commonly used in integrated circuits, show thermally induced stresses due to the difference of the thermal expansion coefficients of the lines and their surroundings. These stresses cause voidage and plastic flow of the lines. Aim of the analysis was to derive equations connecting experimentally measured strains or stresses by the X-ray diffraction and wafer curvature techniques with the magnitude of voidage and plastic shear deformation of the lines.Using the concepts of linear elasticity the volume averaged stresses of an array of parallel interconnects embedded in a passivation layer on a flat substrate are analysed. Equations are derived connecting the volume averaged stresses in the metal and in the passivation with the “eigen-strains” of the metal which characterize the true (stress free) thermal strains and plastic deformation strains of the metal. The coefficients entering these equations are determined from (elastic) finite element method (FEM) calculations performed for various geometries and aspect ratios of the metal lines. Choosing the proper values of the coefficients allows the eigen- strains to be determined from the experimental data.By comparison of the evaluated eigen-strains with the purely elastic eigen-strains ΔaΔT the extent of voidage and/or plastic shear deformation of passivated metal lines caused by thermally induced stresses can be determined model independently.

Finite Element Calculations of Strains in Passivated Metal Lines

1997 ◽  
Vol 473 ◽  
Author(s):  
I. Eppler ◽  
H. Schroeder ◽  
W. Schilling
Keyword(s):  
Finite Element ◽  
Integrated Circuits ◽  
Elastic Constants ◽  
Mean Values ◽  
Thermally Induced ◽  
Thermal Expansion Coefficients ◽  
Parallel Lines ◽  
Finite Element Calculations ◽  
Infinite Array ◽  
Passivated Metal

ABSTRACTPassivated metal lines, commonly used in integrated circuits, show thermally induced strains and stresses due to the mismatch of the thermal expansion coefficients of the lines and their surroundings. These strains depend on the geometry and the elastic constants of both, line and surroundings (i.e. substrate and passivation) and - for the case of an array of parallel lines - on the repetition distance of the lines. For a given set of these parameters the strains and stresses can be obtained from finite element calculations using a model with plane strain conditions.In order to obtain the dependences of the strains from these parameters systematic finite element calculations have been made for an infinite array of parallel lines with variations of the geometries and the elastic constants.Since only the volume mean values of the metal strains can be measured easily (X-ray, wafer curvature method (metal stress)), the dependences of these mean values on the different parameters are presented.

Thermal- And Electromigration- Induced Stresses In Passivated Al- And Alsicu-Interconnects

1996 ◽  
Vol 428 ◽  
Author(s):  
D. Beckers ◽  
H. Schroeder ◽  
I. Eppler ◽  
W. Schilling
Keyword(s):  
Thermal Cycling ◽  
Shear Deformation ◽  
Electronic Devices ◽  
Electrical Current ◽  
Al Alloys ◽  
Plastic Shear ◽  
Stress Evolution ◽  
Experimental Parameters ◽  
Induced Stresses ◽  
Electrical Current Density

AbstractAl and Al- alloys are commonly used as interconnect materials in integrated electronic devices. Stress induced voiding and degradation of metal lines by electromigration are closely related to the stresses in the lines.We have studied the strain and stress evolution during thermal cycling, isothermal relaxation and due to electromigration in passivated Al and AlSi(1%)Cu(0.5%) lines by Xray diffraction with variation of experimental parameters such as the aspect ratio and the electrical current density. Furthermore the extent of voiding and plastic shear deformation has been determined from the experimental metal strains with the help of finite element calculations.Main results are: 1) During thermal cycling the voiding is less than 2.10-3. The extent of plastic shear deformation increases with increasing line width and with decreasing flowstress. 2) During isothermal relaxation void growth occurs but no significant change in the plastic shear deformation. 3) An electric current in the lines causes no measurable additional change of the volume averaged stresses up to line failure.

Thermal Expansion and Relaxation of W-Cu Multilayers

1992 ◽  
Vol 286 ◽  
Author(s):  
Wen-C. Chiang ◽  
Soo-Kil Kim ◽  
David V. Baxter
Keyword(s):  
Thermal Expansion ◽  
High Temperature ◽  
Heat Treatments ◽  
Irreversible Change ◽  
Thermally Induced ◽  
Temperature Range ◽  
Thermal Expansion Coefficients ◽  
Induced Stresses ◽  
Expansion Coefficients ◽  
Bulk Behavior

ABSTRACTWe have studied the structure of W-Cu multilayers with modulation wavelengths between 65 and 110 xsÅ over the temperature range 25-400° C. Using a high temperature diffractometer stage specifically designed for low angle work, thermal expansion coefficients were measured and found to be marginally greater than would be expected from bulk behavior even when interaction with the substrate is taken into account. Upon annealing at temperature as low as 180° C, increased intensity of the low angle superlattice peaks is observed. Heat treatments above 180° C result in an irreversible change in the multilayer associated with the migration of Cu atoms to cracks produced by thermally induced stresses.

Morphologies of Nonadherent Al2O3 and Matching Substrate Surfaces

1972 ◽  
Vol 30 ◽  
pp. 524-525
Author(s):  
C. S. Giggins ◽  
J. K. Tien ◽  
B. H. Kear ◽  
F. S. Pettit
Keyword(s):  
Electron Microscopy ◽  
Oxide Scale ◽  
Oxidation Resistance ◽  
Substrate Surface ◽  
Morphological Features ◽  
Thermally Induced ◽  
Oxide Spallation ◽  
Oxidation Resistant ◽  
Induced Stresses ◽  
Substrate Surfaces

The performance of most oxidation resistant alloys and coatings is markedly improved if the oxide scale strongly adheres to the substrate surface. Consequently, in order to develop alloys and coatings with improved oxidation resistance, it has become necessary to determine the conditions that lead to spallation of oxides from the surfaces of alloys. In what follows, the morphological features of nonadherent Al2O3, and the substrate surfaces from which the Al2O3 has spalled, are presented and related to oxide spallation.The Al2O3, scales were developed by oxidizing Fe-25Cr-4Al (w/o) and Ni-rich Ni3 (Al,Ta) alloys in air at 1200°C. These scales spalled from their substrates upon cooling as a result of thermally induced stresses. The scales and the alloy substrate surfaces were then examined by scanning and replication electron microscopy.The Al2O3, scales from the Fe-Cr-Al contained filamentary protrusions at the oxide-gas interface, Fig. 1(a). In addition, nodules of oxide have been developed such that cavities were formed between the oxide and the substrate, Fig. 1(a).

Detection and Characterization of an Electrical Failure Induced during Laser Ablation of Packages

2008 ◽  
Author(s):  
P. Schwindenhammer ◽  
H. Murray ◽  
P. Descamps ◽  
P. Poirier
Keyword(s):  
Laser Ablation ◽  
Integrated Circuits ◽  
Failure Analysis ◽  
Ablation Process ◽  
Thermally Induced ◽  
Electrical Failure ◽  
Electrical Phenomenon ◽  
Semiconductor Packages ◽  
Complex Semiconductor

Abstract Decapsulation of complex semiconductor packages for failure analysis is enhanced by laser ablation. If lasers are potentially dangerous for Integrated Circuits (IC) surface they also generate a thermal elevation of the package during the ablation process. During measurement of this temperature it was observed another and unexpected electrical phenomenon in the IC induced by laser. It is demonstrated that this new phenomenon is not thermally induced and occurs under certain ablation conditions.

scholarly journals Fabrication of Eutectic Ga-In Nanowire Arrays Based on Plateau–Rayleigh Instability

Molecules ◽  
2021 ◽  
Vol 26 (15) ◽  
pp. 4616
Author(s):  
Takashi Ikuno ◽  
Zen Somei
Keyword(s):  
Integrated Circuits ◽  
Substrate Surface ◽  
Three Dimensional ◽  
Average Diameter ◽  
Nanowire Arrays ◽  
Scanning Probe ◽  
Rayleigh Instability ◽  
Simple Method ◽  
Flat Substrate ◽  
Metal Nanowire

We have developed a simple method of fabricating liquid metal nanowire (NW) arrays of eutectic GaIn (EGaIn). When an EGaIn droplet anchored on a flat substrate is pulled perpendicular to the substrate surface at room temperature, an hourglass shaped EGaIn is formed. At the neck of the shape, based on the Plateau–Rayleigh instability, the EGaIn bridge with periodically varying thicknesses is formed. Finally, the bridge is broken down by additional pulling. Then, EGaIn NW is formed at the surface of the breakpoint. In addition, EGaIn NW arrays are found to be fabricated by pulling multiple EGaIn droplets on a substrate simultaneously. The average diameter of the obtained NW was approximately 0.6 μm and the length of the NW depended on the amount of droplet anchored on the substrate. The EGaIn NWs fabricated in this study may be used for three-dimensional wiring for integrated circuits, the tips of scanning probe microscopes, and field electron emission arrays.

Heat Transfer and Thermal Stress Analysis of an Optoelectronic Package

1991 ◽  
Vol 113 (3) ◽  
pp. 258-262 ◽  
Author(s):  
J. G. Stack ◽  
M. S. Acarlar
Keyword(s):  
Heat Transfer ◽  
Thermal Management ◽  
Power Dissipation ◽  
Point Of View ◽  
Optical Data ◽  
Data Link ◽  
Element Analysis ◽  
Thermally Induced ◽  
Temperature Changes ◽  
Induced Stresses

The reliability and life of an Optical Data Link transmitter are inversely related to the temperature of the LED. It is therefore critical to have efficient packaging from the point of view of thermal management. For the ODL® 200H devices, it is also necessary to ensure that all package seals remain hermetic throughout the stringent military temperature range requirements of −65 to +150°C. For these devices, finite element analysis was used to study both the thermal paths due to LED power dissipation and the thermally induced stresses in the hermetic joints due to ambient temperature changes

Thermally Induced Delamination Buckling of a Thin Metal Layer on a Ceramic Substrate

2003 ◽  
Vol 125 (4) ◽  
pp. 512-519 ◽  
Author(s):  
C. J. Liu ◽  
L. J. Ernst ◽  
G. Wisse ◽  
G. Q. Zhang ◽  
M. Vervoort
Keyword(s):  
Failure Modes ◽  
Research Effort ◽  
Metal Layer ◽  
Electronic Packages ◽  
Ceramic Substrates ◽  
Thermally Induced ◽  
Thermal Expansion Coefficients ◽  
Interface Delamination ◽  
Delamination Buckling ◽  
Expansion Coefficients

Interface delamination failure caused by thermomechanical loading and mismatch of thermal expansion coefficients and other material properties is one of the important failure modes occurring in electronic packages, thus a threat for package reliability. To solve this problem, both academic institutions and industry have been spending tremendous research effort in order to understand the inherent failure mechanisms and to develop advanced and reliable experimental and simulation methodologies, thus to be able to predict and to avoid interface delamination before physical prototyping. Various damage mechanisms can be involved and can result in interface delamination phenomena. These are not all sufficiently addressed and/or reported so far, probably because of the complexities caused by the occurrence of strong geometric and materials nonlinearities. One of the phenomena being insufficiently understood so far is the so-called buckling-driven delamination of thin metalic layers on ceramic substrates. This phenomenon will be discussed in the present paper.

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