Defect and Band Gap Engineering of Amorphous Silicon Solar Cells

1993 ◽  
Vol 297 ◽  
Author(s):  
R.E.I. Schropp ◽  
J.Daey Ouwens ◽  
M.B. Von Der Linden ◽  
C.H.M. Von Der Werf ◽  
W.F. Van Der Weg ◽  
...  

This paper demonstrates that the incorporation of an unoptimized, wide band gap a-SiC:H layer near the p-type emitter layer in addition to a graded bandgap ”buffer” layer, leads to improved fill factors and open circuit voltages, in spite of the increased number of recombination sites at the p/i heterojunction. The as deposited as a function of a-SiC:H thickness shows an optimum of 10.5 % at a thickness of 10 – 20 Å. We have further improved this type of cell by incorporating a reverse carbon graded p-type layer and have thus achieved efficiencies in excess of 11.0 %. The cells are all amorphous and do not comprise antireflective coatings or enhanced back reflectors. A new defect engineering scheme to accomplish enhanced stabilized efficiencies of amorphous silicon solar cells is also proposed here.

Energies ◽  
2021 ◽  
Vol 15 (1) ◽  
pp. 4
Author(s):  
Dwinanri Egyna ◽  
Kazuyoshi Nakada ◽  
Akira Yamada

Despite the potential in single- and multi-junction solar cells application, research into the wide band gap CuIn1−xGax(Se1−ySy)2 or CIG(SSe)2 solar cell material, with Eg≥1.5eV, has yet to be extensively performed to date. In this work, we conducted a numerical study into the role of the n-type layers in CIG(SSe)2 heterojunction solar cells, specifically concerning the maximum open-circuit voltage of the devices. In the first part of the study, we derived a new ideal open-circuit voltage equation for a thin-film heterojunction solar cell by taking into account the current contribution from the depletion region. The accuracy of the new equation was validated through a simulation model in the second part of the study. Another simulation model was also used to clarify the design rules of the n-type layer in a wide band gap CIG(SSe)2 solar cell. Our work stressed the importance of a positive conduction band offset on the n-/p-type interface, through the use of a low electron affinity n-type material for a solar cell with a high open-circuit voltage . Through a precise selection of the window layer material, a buffer-free CIG(SSe)2 design is sufficient to fulfill such conditions. We also proposed the specific roles of the n-type layer, i.e., as a passivation layer and selective electron contact, in the operation of CIGS2 solar cells.


1996 ◽  
Author(s):  
Yasuhiro Matsumoto ◽  
René Asomoza ◽  
Gustavo Hirata ◽  
Leonel Cota-Araiza

2007 ◽  
Vol 101 (11) ◽  
pp. 114301 ◽  
Author(s):  
J. M. Pearce ◽  
N. Podraza ◽  
R. W. Collins ◽  
M. M. Al-Jassim ◽  
K. M. Jones ◽  
...  

2015 ◽  
Vol 9 (8) ◽  
pp. 453-456 ◽  
Author(s):  
Shuo Wang ◽  
Vladimir Smirnov ◽  
Tao Chen ◽  
Xiaodan Zhang ◽  
Shaozhen Xiong ◽  
...  

2006 ◽  
Vol 910 ◽  
Author(s):  
Qi Wang ◽  
Matt P. Page ◽  
Eugene Iwancizko ◽  
Yueqin Xu ◽  
Yanfa Yan ◽  
...  

AbstractWe have achieved an independently-confirmed 17.8% conversion efficiency in a 1-cm2, p-type, float-zone silicon (FZ-Si) based heterojunction solar cell. Both the front emitter and back contact are hydrogenated amorphous silicon (a-Si:H) deposited by hot-wire chemical vapor deposition (HWCVD). This is the highest reported efficiency for a HWCVD silicon heterojunction (SHJ) solar cell. Two main improvements lead to our most recent increases in efficiency: 1) the use of textured Si wafers, and 2) the application of a-Si:H heterojunctions on both sides of the cell. Despite the use of textured c-Si to increase the short-circuit current, we were able to maintain the same 0.65 V open-circuit voltage as on flat c-Si. This is achieved by coating a-Si:H conformally on the c-Si surfaces, including covering the tips of the anisotropically-etched pyramids. A brief atomic H treatment before emitter deposition is not necessary on the textured wafers, though it was helpful in the flat wafers. It is essential to high efficiency SHJ solar cells that the emitter grows abruptly as amorphous silicon, instead of as microcrystalline or epitaxial Si. The contact on each side of the cell comprises a thin (< 5 nm) low substrate temperature (~100°C) intrinsic a-Si:H layer, followed by a doped layer. Our intrinsic layers are deposited at 0.3-1.2 nm/s. The doped emitter and back-contact layers were deposited at a higher temperature (>200°C) and grown from PH3/SiH4/H2 and B2H6/SiH4/H2 doping gas mixtures, respectively. This combination of low (intrinsic) and high (doped layer) growth temperatures was optimized by lifetime and surface recombination velocity measurements. Our rapid efficiency advance suggests that HWCVD may have advantages over plasma-enhanced (PE) CVD in fabrication of high-efficiency heterojunction c-Si cells; there is no need for process optimization to avoid plasma damage to the delicate, high-quality, Si wafers.


2015 ◽  
Vol 5 (6) ◽  
pp. 1757-1761 ◽  
Author(s):  
Daniel Amkreutz ◽  
William D. Barker ◽  
Sven Kuhnapfel ◽  
Paul Sonntag ◽  
Onno Gabriel ◽  
...  

2020 ◽  
Vol 12 (23) ◽  
pp. 26184-26192 ◽  
Author(s):  
Shuangying Cao ◽  
Dongliang Yu ◽  
Yinyue Lin ◽  
Chi Zhang ◽  
Linfeng Lu ◽  
...  

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