Accelerated Degradation Mechanisms in Amorphous Silicon Thin Film Transistors

1992 ◽  
Vol 284 ◽  
Author(s):  
I. J. Chung ◽  
C. H. Oh ◽  
W. Y. Kim ◽  
J. R. Hwang ◽  
Y. S. Kim ◽  
...  
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Early Stage ◽  
Charge Trapping ◽  
Light Illumination ◽  
Silicon Thin Film ◽  
Accelerated Degradation ◽  
Electrical Stress ◽  
Defect Creation

ABSTRACTThe accelerated degradation phenomena in amorphous silicon thin film transistors due to both electrical stress and visible light illumination under the elevated temperature have been investigated systematically as a function of gate bias, light intensity, and stress time. It has been found that, in case of electrical stress, the threshold voltage shifts of a-Si TFT's may be attributed to the defect creation process at the early stage, while the charge trapping phenomena may be dominant when the illumination periods exceed about 2 hours. It has been also observed that the degradation in the device characteristics of a-Si TFT's is accelerated due to multiple stress effects, where the defect creation mechanism may be more responsible for the degradation rather than the charge trapping mechanism.

Effects of Temperature and Electrical Stress on the Characteristics of Amorphous Silicon Thin-Film Transistors

1991 ◽  
Vol 219 ◽  
Author(s):  
Jin S. Park ◽  
Chang H. Oh ◽  
Hong S. Choi ◽  
Min K. Han ◽  
Yearn I. Choi ◽  
...  
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Charge Trapping ◽  
Experimental Results ◽  
Silicon Thin Film ◽  
Electrical Stress ◽  
Interface Charge ◽  
Temperature Ranges ◽  
Effects Of Temperature

ABSTRACTThe experimental and analytical results regarding to the effects of temperature and electrical stress on the characteristics of amorphous silicon thin-film transistors (a-Si TFT's) have been presented. The variations in the device parameters of a-Si TFT, such as threshold voltage and field-effect mobility, have been examined under various operating temperatures and electrical stress conditions. The hysteresis in the transfer characteristics and the trapped charges at the a-Si/silicon nitride interface were measured at the operating temperature ranges. From the experimental results, it has been found out that the increase of the interface charge trapping may be responsible for the degradation in the a-Si TFT characteristics. Also, an analytical formulation, employing the interface charge trapping, is presented to clarify the instability phenomena and verified successfully with the experimental results.

Threshold Voltage Shifts in Amorphous Silicon Thin Film Transistors under Bias Stress

1990 ◽  
Vol 192 ◽  
Author(s):  
Tetsu Ogawa ◽  
Sadayoshi Hotta ◽  
Horoyoshi Takezawa
Keyword(s):  
Thin Film ◽  
Temperature Dependence ◽  
Amorphous Silicon ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Charge Trapping ◽  
The Other ◽  
Time Dependent ◽  
Silicon Thin Film ◽  
Bias Stress

ABSTRACTThrough the time and temperature dependence measurements on threshold voltage shifts (Δ VT) in amorphous silicon thin film transistors, it has been found that two separate instability mechanisms exist; within short stress time ranges Δ Vτ increases as log t and this behavior corresponds to charge trapping in SiN. On the other hand, in long stress time ranges Δ VT increases as t t/4 and can be explained by time-dependent creation of trap in a-Si.

Defect creation in amorphous-silicon thin-film transistors

1995 ◽  
Vol 52 (7) ◽  
pp. 4680-4683 ◽  
Author(s):  
C. F. O. Graeff ◽  
M. S. Brandt ◽  
M. Stutzmann ◽  
M. J. Powell
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Silicon Thin Film ◽  
Defect Creation

Kinetics of defect creation in amorphous silicon thin film transistors

2003 ◽  
Vol 93 (9) ◽  
pp. 5780-5788 ◽  
Author(s):  
R. B. Wehrspohn ◽  
M. J. Powell ◽  
S. C. Deane
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Silicon Thin Film ◽  
Defect Creation ◽  
Kinetics Of

Effects of Top Insulator Overlap on the Stability in Hydrogenated Amorphous Silicon Thin Film Transistors

1994 ◽  
Vol 336 ◽  
Author(s):  
H.S. Choi ◽  
Y.S. Kim ◽  
S.K. Lee ◽  
J.K. Yoon ◽  
W.S. Park ◽  
...  
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Hydrogenated Amorphous Silicon ◽  
Charge Trapping ◽  
Channel Length ◽  
Gate Insulator ◽  
Silicon Thin Film ◽  
Bias Stress ◽  
Hydrogenated Amorphous

ABSTRACTThe effects of top-insulator on the instability problems of hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs) have been studied. In a-Si:H TFT with top-insulator (E/S type), charge trapping into the both of top-insulator and gate insulator has been shown under the bias stress.In order to investigate the charge trapping effects of top-insulator, we proposed a new method of Measurement. By this Method, we observed that trapped charges in top-insulator increased drain currents for positive gate bias stress, and this increment of drain currents was more serious with increasing the ratio of source/drain overlap length to channel length. It has founded that the instability problems of a-Si:H TFTs was attributed to the effects of top-insulator as well as that of gate insulator.

The Instability Characteristics of Amorphous Silicon Thin Film Transistors with Various Interfacial and Bulk Defect States

1997 ◽  
Vol 36 (Part 1, No. 10) ◽  
pp. 6226-6229 ◽  
Author(s):  
Huang-Chung Cheng ◽  
Jun-Wei Tsai ◽  
Chun-Yao Huang ◽  
Fang-Chen Luo ◽  
Hsing-Chien Tuan
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Defect States ◽  
Silicon Thin Film

Hot-Wire Deposited Amorphous Silicon Thin-Film Transistors

1996 ◽  
Vol 424 ◽  
Author(s):  
R. E. I. Schropp ◽  
K. F. Feenstra ◽  
C. H. M. Van Der Werf ◽  
J. Holleman ◽  
H. Meiling
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Chemical Vapor ◽  
Current Crowding ◽  
Hot Wire ◽  
Saturation Regime ◽  
Silicon Thin Film ◽  
Order Of Magnitude

AbstractWe present the first thin film transistors (TFTs) incorporating a low hydrogen content (5 - 9 at.-%) amorphous silicon (a-Si:H) layer deposited by the Hot-Wire Chemical Vapor Deposition (HWCVD) technique. This demonstrates the possibility of utilizing this material in devices. The deposition rate by Hot-Wire CVD is an order of magnitude higher than by Plasma Enhanced CVD. The switching ratio for TFTs based on HWCVD a-Si:H is better than 5 orders of magnitude. The field-effect mobility as determined from the saturation regime of the transfer characteristics is still quite poor. The interface with the gate dielectric needs further optimization. Current crowding effects, however, could be completely eliminated by a H2 plasma treatment of the HW-deposited intrinsic layer. In contrast to the PECVD reference device, the HWCVD device appears to be almost unsensitive to bias voltage stressing. This shows that HW-deposited material might be an approach to much more stable devices.

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