Insulating and Breakdown Characteristics of Low Temperature GaAs

1991 ◽  
Vol 241 ◽  
Author(s):  
H. L. Grubin ◽  
J. P. Kreskovsky ◽  
R. Levy
Keyword(s):  
Numerical Simulation ◽  
Low Temperature ◽  
Valence Band ◽  
Conduction Band ◽  
Electrical Characteristics ◽  
Simulation Techniques ◽  
Low Temperature Gaas ◽  
High Donor

ABSTRACTThe electrical characteristics of an N(LT)N structure are studied through implementation of numerical simulation techniques for the case of donor traps 0.83 ev below the conduction band and acceptor traps 0.3 ev above the valence band. The results show characteristics sensitive to the relative densities of the traps. In particular, high acceptor trap / low donor trap concentrations generally result in low breakdown voltages, whereas high acceptor / high donor concentrations result in higher breakdown voltages.

Photoemission study of the valence band offset between low temperature GaAs and (GaMn)As

2006 ◽  
Vol 89 (17) ◽  
pp. 172509 ◽  
Author(s):  
M. Adell ◽  
J. Adell ◽  
L. Ilver ◽  
J. Kanski ◽  
J. Sadowski
Keyword(s):  
Low Temperature ◽  
Valence Band ◽  
Band Offset ◽  
Valence Band Offset ◽  
Photoemission Study ◽  
Low Temperature Gaas

The Visible and the Infrared Luminescence Bands as a Tool for Characterization of the Porous Silicon Bandstructure

1994 ◽  
Vol 358 ◽  
Author(s):  
V. Petrova-Koch ◽  
T. Muschik ◽  
G. Polisski ◽  
D. Kovalev
Keyword(s):  
Porous Silicon ◽  
Low Temperature ◽  
Valence Band ◽  
Conduction Band ◽  
Porous Si ◽  
Surface Degradation ◽  
Infrared Luminescence

ABSTRACTThe visible and the infrared photoluminescence bands in porous Si have been studied at low temperature for two series of samples: one in which the size of the crystallites has been varied and another in which the degree of surface degradation has been changed. It is shown that the relation of the two bands can be explored for characterization of the porous Si bandstructure. The size- and the surface dependence of the valence band and of the conduction band related states is discussed. A model is proposed for explanation.

scholarly journals Effect of Interface Traps on the RTS Noise Behavior of Junctionless Nanowires

2020 ◽  
Vol 15 (2) ◽  
pp. 1-5
Author(s):  
Marcos Picoli ◽  
Renan Trevisoli ◽  
Rodrigo T. Doria
Keyword(s):  
Experimental Data ◽  
Numerical Simulation ◽  
Valence Band ◽  
Conduction Band ◽  
Exponential Model ◽  
Interface Traps ◽  
Random Telegraph Signal ◽  
Single Interface ◽  
Rts Noise ◽  
Junctionless Nanowire Transistor

This work presents a study on the effects of single interface traps throughout the Junctionless Nanowire Transistor (JNT). The results are obtained by analyzing the Random Telegraph Signal noise of the device, which consists of an exception of the generation-recombination noise. The results obtained are mostly from numerical simulation, validated through experimental data. As in physical devices, it is impossible to obtain a single trap in specific locations, we have used a distribution of traps with similar characteristics in a way that they behave like a single trap. The results show the behave considering a set of traps distributions, using an exponential model. The traps are distributed from the conduction band to the valence band. Keywords– JNT; RTS Noise; G-r Noise; Interface Traps.  

Simulation and Modeling of Turbulent Flows

1996 ◽  
Keyword(s):  
Numerical Simulation ◽  
Turbulent Flow ◽  
Turbulent Flows ◽  
Simulation And Modeling ◽  
Simulation Techniques ◽  
Rational Development ◽  
Group Methods ◽  
Turbulent Closure ◽  
The Subject ◽  
Renormalization Group Methods

This book provides students and researchers in fluid engineering with an up-to-date overview of turbulent flow research in the areas of simulation and modeling. A key element of the book is the systematic, rational development of turbulence closure models and related aspects of modern turbulent flow theory and prediction. Starting with a review of the spectral dynamics of homogenous and inhomogeneous turbulent flows, succeeding chapters deal with numerical simulation techniques, renormalization group methods and turbulent closure modeling. Each chapter is authored by recognized leaders in their respective fields, and each provides a thorough and cohesive treatment of the subject.

Study of Modulation in GaAs Misfets with LT-GaAs as a Gate Insulator

1991 ◽  
Vol 241 ◽  
Author(s):  
L.-W. Yin ◽  
J. Ibbetson ◽  
M. M. Hashemi ◽  
W. Jiang ◽  
S.-Y. Hu ◽  
...  
Keyword(s):  
Low Temperature ◽  
Gaas Layer ◽  
Gate Insulator ◽  
Gate Bias ◽  
Channel Current ◽  
Turn On ◽  
Dc Characteristics ◽  
Low Temperature Gaas ◽  
Channel Separation ◽  
Lt Gaas

ABSTRACTDC characteristics of a GaAs MISFET structure using low-temperature GaAs (LTGaAs) as the gate insulator were investigated. MISFETs with different gate to channel separation (d) were fabricated. The dependence of four important device parameters such as gate-drain breakdown voltage (VBR), channel current at zero gate bias (Idss), transconductance (gm), and gate-drain turn-on voltage (Von) on the gate insulator thickness were analyzed. It was observed that (a) in terms of Idss and gin, the LT-GaAs gate insulator behaves like an undoped regular GaAs layer and (b) in terms of VBR and Von, the LT-GaAs gate insulator behaves as a trap dominated layer.

Electrical Characterization of Low Temperature GaAs Layers, and Observation of the Extremely Large Carrier Concentrations in Undoped Material

1991 ◽  
Vol 241 ◽  
Author(s):  
Bijan Tadayon ◽  
Mohammad Fatemi ◽  
Saied Tadayon ◽  
F. Moore ◽  
Harry Dietrich
Keyword(s):  
Molecular Beam Epitaxy ◽  
Low Temperature ◽  
Substrate Temperature ◽  
Molecular Beam ◽  
Electrical Characterization ◽  
Physical Characteristics ◽  
Hall Measurements ◽  
Undoped Material ◽  
Low Temperature Gaas

ABSTRACTWe present here the results of a study on the effect of substrate temperature, Ts, on the electrical and physical characteristics of low temperature (LT) molecular beam epitaxy GaAs layers. Hall measurements have been performed on the asgrown samples and on samples annealed at 610 °C and 850 °C. Si implantation into these layers has also been investigated.

Low temperature GaAs/Si direct wafer bonding

2000 ◽  
Vol 36 (7) ◽  
pp. 677 ◽  
Author(s):  
M. Alexe ◽  
V. Dragoi ◽  
M. Reiche ◽  
U. Gösele
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
Direct Wafer Bonding ◽  
Low Temperature Gaas

Low-temperature-GaAs device used simultaneously as a mode-locking device and as a photoconductive switch

2002 ◽  
Vol 41 (12) ◽  
pp. 2228
Author(s):  
Martin Leitner ◽  
Peter Glas ◽  
Peter Semionyk ◽  
Marc Wrage ◽  
Jens Herfort ◽  
...  
Keyword(s):  
Low Temperature ◽  
Mode Locking ◽  
Photoconductive Switch ◽  
Low Temperature Gaas
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