Defect-Characterization in Implanted Locos + Trench-Isolated Structures

1991 ◽  
Vol 239 ◽  
Author(s):  
N. David Theodore ◽  
Barbara Vasquez ◽  
Peter Fejes
Keyword(s):  
Integrated Circuits ◽  
Cross Section ◽  
High Dose ◽  
Defect Characterization ◽  
Dislocation Loops ◽  
Etch Pits ◽  
Local Oxidation ◽  
Silicon Integrated Circuits ◽  
Trench Isolation ◽  
Dislocation Sources

ABSTRACTAs device dimensions decrease in silicon integrated-circuits, conventional LOCOS (local-oxidation of silicon) isolation becomes inadequate to meet dimensional demands. Variations on LOCOS are therefore being explored for further miniaturization of devices. One such variation involves poly-buffered LOCOS + trench-isolation (PBLT). In this study, PBLT structures were characterized using TEM. Wright-etched cross-section SEM micrographs showed etch-pits associated with a combination of high-dose (> 5E14 cm-2) phosphorous implants and PBLT isolation. TEM characterization showed that dislocations were formed in the structures for a combination of high-dose (1E15 cm-2) phosphorous implants (followed by an anneal) and PBLT isolation. Structures exposed to lower-dose (1E14 cm-2) implants showed no defects and neither did 1E15 implanted structures prior to annealing. The results are modelled in terms of the stress configurations present in the structures, and in terms of dislocation-sources resulting from implantation-related dislocation-loops. The dislocation-sources operate in the presence of stresses associated with the isolation-trenches. Glide-loops form, which then grow in response to stresses in the structures and dislocations result on glide planes.

Stress-Related Defects in Implanted Locos + Trench - Isolated Structures

1992 ◽  
Vol 262 ◽  
Author(s):  
Barbara Vasquez ◽  
N. David Theodore
Keyword(s):  
Stress Fields ◽  
High Dose ◽  
Extended Defects ◽  
Dislocation Loops ◽  
Defect Engineering ◽  
Local Oxidation ◽  
Trench Isolation ◽  
And Behavior ◽  
Dislocation Sources ◽  
Reducing Stress

ABSTRACTPoly-buffered local-oxidation of silicon + trench-isolation (PBLT) is a technique being explored for device isolation. In an earlier study, we had reported the presence of dislocations associated with a combination of high-dose (∼5E14 cm2) phosphorous implants and PBLT isolation. In the present study, the behavior of extended defects present in the structures is analyzed in greater detail. The origin and behavior of the defects is modelled to explore potential mechanisms to explain the observations. Implantation induced dislocation-loops interact with stress fields associated with PBLT isolation-trenches. Some of the implant loops (in the presence of a stress field) transform to dislocation sources which then create glide dislocations in the structures. Strategies for defect engineering are discussed, including reducing implant-induced damage (lowering the implant dose) or reducing stress fields (by moving the edge of the implanted region away from the trench). Defect densities can be reduced or eliminated.

Formation of defects in implanted hipox-structures

1992 ◽  
Vol 50 (2) ◽  
pp. 1406-1407
Author(s):  
Peter Pegler ◽  
N. David Theodore ◽  
Ming Pan
Keyword(s):  
High Pressure ◽  
Cross Section ◽  
Semiconductor Devices ◽  
Silicon Substrates ◽  
Processing Conditions ◽  
Pressure Oxidation ◽  
Deep Trench ◽  
Local Oxidation ◽  
Trench Isolation ◽  
And Behavior

High-pressure oxidation of silicon (HIPOX) is one of various techniques used for electrical-isolation of semiconductor-devices on silicon substrates. Other techniques have included local-oxidation of silicon (LOCOS), poly-buffered LOCOS, deep-trench isolation and separation of silicon by implanted oxygen (SIMOX). Reliable use of HIPOX for device-isolation requires an understanding of the behavior of the materials and structures being used and their interactions under different processing conditions. The effect of HIPOX-related stresses in the structures is of interest because structuraldefects, if formed, could electrically degrade devices.This investigation was performed to study the origin and behavior of defects in recessed HIPOX (RHIPOX) structures. The structures were exposed to a boron implant. Samples consisted of (i) RHlPOX'ed strip exposed to a boron implant, (ii) recessed strip prior to HIPOX, but exposed to a boron implant, (iii) test-pad prior to HIPOX, (iv) HIPOX'ed region away from R-HIPOX edge. Cross-section TEM specimens were prepared in the <110> substrate-geometry.

Highlights in the history of X-ray topography1

1995 ◽  
Vol 210 (6) ◽  
Author(s):  
A. R. Lang
Keyword(s):  
Magnetic Domain ◽  
Diffraction Theory ◽  
Dislocation Loops ◽  
X Ray Diffraction ◽  
X Ray ◽  
Domain Structures ◽  
Structure Factors ◽  
History Of ◽  
Dislocation Sources ◽  
Non Destructive

AbstractX-ray topography provides a non-destructive method of mapping point-by-point variations in orientation and reflecting power within crystals. The discovery, made by several workers independently, that in nearly perfect crystals it was possible to detect individual dislocations by X-ray diffraction contrast started an epoch of rapid exploitation of X-ray topography as a new, general method for assessing crystal perfection. Another discovery, that of X-ray Pendellösung, led to important theoretical developments in X-ray diffraction theory and to a new and precise method for measuring structure factors on an absolute scale. Other highlights picked out for mention are studies of Frank-Read dislocation sources, the discovery of long dislocation helices and lines of coaxial dislocation loops in aluminium, of internal magnetic domain structures in Fe-3 wt.% Si, and of stacking faults in silicon and natural diamonds.

Electrical Invasiveness of Grinding and Polishing Silicon Integrated Circuits Down to 1 μm Remaining Silicon Thickness

2016 ◽  
Author(s):  
Robert Chivas ◽  
Scott Silverman ◽  
Michael DiBattista ◽  
Ulrike Kindereit
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Electron Hole ◽  
Analysis Techniques ◽  
Silicon Integrated Circuits ◽  
Electron Hole Pair ◽  
Pair Generation ◽  
Silicon Thickness ◽  
Performance Timing ◽  
Grinding And Polishing

Abstract Anticipating the end of life for IR-based failure analysis techniques, a method of global backside preparation to ultra-thin remaining silicon thickness (RST) has been developed. When the remaining silicon is reduced, some redistribution of stress is expected, possibly altering the performance (timing) of integrated circuits in addition to electron-hole pair generation. In this work, a study of the electrical invasiveness due to grinding and polishing silicon integrated circuits to ultra-thin (&lt; 5 um global, ~ 1 um local) remaining thickness is presented.

TEM investigation of defect reduction and etch pit formation in GaN

2003 ◽  
Vol 798 ◽  
Author(s):  
Angelika Vennemann ◽  
Jens Dennemarck ◽  
Roland Kröger ◽  
Tim Böttcher ◽  
Detlef Hommel ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Dislocation Density ◽  
Line Tension ◽  
Threading Dislocations ◽  
Dislocation Loops ◽  
Etch Pits ◽  
Defect Reduction ◽  
Transmission Electron ◽  
Order Of Magnitude ◽  
Edge Dislocations

ABSTRACTGaN samples of this study were chemically wet etched to gain easier access to the dislocation sturcture. The scanning electron microscopy and transmission electron microscopy investigations revealed four different types of etch pits. After brief etching, several dislocations with screw component showed large etch pits, which may be correlated with the core of the screw dislocation. By means of SiNx micromasking the dislocation density could be reduced by more than one order of magnitude. The reduction of threading dislocations in the SiNx region in GaN grown on 〈0001〉 sapphire is due to bending of the threading dislocations into the {0001} plane, such that they form dislocation loops if they meet dislocations with opposite Burgers vectors. Accordingly, the achievable reduction of the dislocation density is limited by the probability that these dislocations interact. Edge dislocations bend more easily on account of their low line tension. This results in a preferential bending and reduction of dislocations with edge character.

Laser cross section measurement for the evaluation of single-event effects in integrated circuits

2000 ◽  
Vol 40 (8-10) ◽  
pp. 1371-1375 ◽  
Author(s):  
V. Pouget ◽  
P. Fouillat ◽  
D. Lewis ◽  
H. Lapuyade ◽  
F. Darracq ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Cross Section ◽  
Single Event ◽  
Cross Section Measurement ◽  
Single Event Effects ◽  
Section Measurement

Electro‐optic sampling of high‐speed silicon integrated circuits using a GaAs probe tip

1991 ◽  
Vol 59 (2) ◽  
pp. 146-148 ◽  
Author(s):  
Michael S. Heutmaker ◽  
George T. Harvey ◽  
Philip F. Bechtold
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Electro Optic ◽  
Silicon Integrated Circuits
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