Metal-Ferroelectric-Semiconductor Characteristics of BaMgF4 Films on p-Silicon

1991 ◽  
Vol 230 ◽  
Author(s):  
T. S. Kalkur ◽  
J. R. Kulkarni ◽  
R. Y. Kwor ◽  
L. Levinson ◽  
L. Kammerdiner
Keyword(s):  
Threshold Voltage ◽  
Zirconium Oxide ◽  
Ionic Conduction ◽  
Electrical Characterization ◽  
Temperature Dependent ◽  
Capping Layer ◽  
Capacitance Voltage ◽  
Ferroelectric Memories ◽  
Non Destructive

AbstractCapacitance-voltage characterstics of BaMgF4 film deposited in an ion-assisted deposition system shows hysteresis and the direction of hysteresis corresponds to ferroelectric polarization. Electrical characterization of the films shows that these films can be used to implement non-destructive read-out non-volatile ferroelectric memories. These films were found to dissolve in water and other aqueous solutions. In order to overcome this problem, a suitable capping layer like zirconium oxide and amorphous silicon was deposited on BMF films. The shift in threshold voltage did not change significantly due to the incorporation of the capping layer. The shift in threshold voltage was found to be temperature dependent and this might be due to ionic conduction in fluorides.

Analysis of an Anomalous CMOS Transistor Exhibiting Drain to Source Leakage—Its Model and Cause

2014 ◽  
Author(s):  
Yuk L. Tsang ◽  
Alex VanVianen ◽  
Xiang D. Wang ◽  
N. David Theodore
Keyword(s):  
Threshold Voltage ◽  
Crystalline Silicon ◽  
Electrical Characterization ◽  
Visual Defect ◽  
Scanning Capacitance Microscopy ◽  
Device Model ◽  
Graphical Simulation ◽  
Cmos Transistor

Abstract In this paper, we report a device model that has successfully described the characteristics of an anomalous CMOS NFET and led to the identification of a non-visual defect. The model was based on detailed electrical characterization of a transistor exhibiting a threshold voltage (Vt) of about 120mv lower than normal and also exhibiting source to drain leakage. Using a simple graphical simulation, we predicted that the anomalous device was a transistor in parallel with a resistor. It was proposed that the resistor was due to a counter doping defect. This was confirmed using Scanning Capacitance Microscopy (SCM). The dopant defect was shown by TEM imaging to be caused by a crystalline silicon dislocation.

Analysis of an Anomalous Transistor Exhibiting Dual-Vt Characteristics and Its Cause in a 90nm Node CMOS Technology

2012 ◽  
Author(s):  
Yuk L. Tsang ◽  
Xiang D. Wang ◽  
Reyhan Ricklefs ◽  
Jason Goertz
Keyword(s):  
Threshold Voltage ◽  
Electrical Characterization ◽  
Cmos Technology ◽  
Short Channel ◽  
Visual Defect ◽  
Subthreshold Region ◽  
Short Channel Effect ◽  
Channel Effect ◽  
Transistor Model

Abstract In this paper, we report a transistor model that has successfully led to the identification of a non visual defect. This model was based on detailed electrical characterization of a MOS NFET exhibiting a threshold voltage (Vt) of just about 40mv lower than normal. This small Vt delta was based on standard graphical extrapolation method in the usual linear Id-Vg plots. We observed, using a semilog plot, two slopes in the Id-Vg curves with Vt delta magnified significantly in the subthreshold region. The two slopes were attributed to two transistors in parallel with different Vts. We further found that one of the parallel transistors had short channel effect due to a punch-through mechanism. It was proposed and ultimately confirmed the cause was due to a dopant defect using scanning capacitance microscopy (SCM) technique.

Temperature dependent optical and electrical characterization of SnS/CdS solar cell.

2021 ◽  
pp. 139069
Author(s):  
Taavi Raadik ◽  
Nicolae Spalatu ◽  
Jüri Krustok ◽  
Raavo Josepson ◽  
Maarja Grossberg
Keyword(s):  
Solar Cell ◽  
Electrical Characterization ◽  
Temperature Dependent

Electrical Characterization of In Schottky Contacts to Epitaxial n-In0.46Ga0.54P Grown on n+-GaAs by Mocvd

1996 ◽  
Vol 448 ◽  
Author(s):  
N. Marcano ◽  
A. Singh
Keyword(s):  
Barrier Height ◽  
Thermionic Emission ◽  
Electrical Characterization ◽  
Interface Layer ◽  
Zero Bias ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Direct Current Voltage ◽  
Etched Surface

AbstractIn/n-In0.46Ga0.54P Schottky diode was fabricated by thermal evaporation of In on chemically etched surface of In0.45Ga0.54P:Si epitaxial layer grown on highly doped n type GaAs. The In metal formed a high quality rectifying contact to In0.46Ga0.54P:Si with a rectification ratio of 500. The direct current-voltage/temperature (I-V/T) characteristics were non-ideal with the values of the ideality factor (n) between 1.26-1.78 for 400>T>260 K. The forward I-V data strongly indicated that the current was controlled by the generation-recombination (GR) and thermionic emission (TE) mechanisms for temperature in the range 260-400 K. From the temperature variation of the TE reverse saturation current, the values of (0.75±0.05)V and the (4.5±0.5)×10-5 Acm-2K-2 for the zero bias zero temperature barrier height (φoo) and modified effective Richardson constant were obtained. The 1 MHz capacitance-voltage (C-V) data for 260 K < T < 400 K was analyzed in terms of the C-2-V relation including the effect of interface layer to obtain more realistic values of the barrier height (φbo). The temperature dependence of φbo was described the relation φbo =(0.86±10.03) - (8.4±0.7)×l0-4T. The values of φoo, obtained by the I-V and C-V techniques agreed well.

Contact-Less Electrical Defect Characterization of Semi-Insulating 6H-SiC Bulk Material

2008 ◽  
Vol 600-603 ◽  
pp. 405-408 ◽  
Author(s):  
S. Hahn ◽  
Franziska Christine Beyer ◽  
Andreas Gällström ◽  
Patrick Carlsson ◽  
Anne Henry ◽  
...  
Keyword(s):  
Bulk Material ◽  
Electrical Characterization ◽  
The Novel ◽  
Spatially Resolved ◽  
Peak Assignment ◽  
Shallow Defect ◽  
Defect Levels ◽  
Transient Spectroscopy ◽  
Non Destructive

The novel technique microwave detected photo induced current transient spectroscopy (MD-PICTS) was applied to semi-insulating 6H-SiC in order to investigate the properties of inherent defect levels. Defect spectra can be obtained in the similar way to conventional PICTS and DLTS. However, there is no need for contacting the samples, which allows for non-destructive and spatially resolved electrical characterization. This work is focused on the investigation of semi-insulating 6H-SiC grown under different C/Si-ratios. In the corresponding MD-PICTS spectra several shallow defect levels appear in the low temperature range. However the peak assignment needs further investigation. Additionally different trap reemission dynamics are obtained for higher temperatures, which are supposed to be due to different compensation effects.

Electrical Characterization of Al2O3 - SiO2 Mos Structures

1999 ◽  
Vol 567 ◽  
Author(s):  
L-Å Ragnarsson ◽  
E. Aderstedt ◽  
P. Lundgren
Keyword(s):  
Electrical Characterization ◽  
Thickness Reduction ◽  
Initial Thickness ◽  
Equivalent Thickness ◽  
Conventional Furnace ◽  
Capacitance Voltage ◽  
Layered Dielectric ◽  
The Impact ◽  
Mos Structures

ABSTRACTA comparative capacitance voltage method is used to investigate the equivalent thickness reduction during post metallization annealing of thermally grown ultrathin (∼15-27 Å) oxides. It is found that a double layered dielectric consisting of a thin Al2O3—SiO2 sandwich is appropriate to describe both the increased capacitance and the nearly unaltered current after anneal. It is further shown that the impact of initial thickness and method of growth — in a conventional furnace or by rapid thermal oxidation — on the equivalent thickness reduction is negligible.

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