Titania/Silica Sol-Gel Films: Comparison of Techniques for Thin Film Thickness Measurement

1990 ◽  
Vol 180 ◽  
Author(s):  
S. M. Melpolder ◽  
A. W. West ◽  
M. P. Cunningham ◽  
R. Sharma
Keyword(s):  
Thin Film ◽  
Sol Gel ◽  
Thickness Measurement ◽  
Silica Sol ◽  
Cross Sectional ◽  
Advantages And Disadvantages ◽  
Transmission Electron ◽  
Comparison Of Techniques ◽  
Sol Gel Films ◽  
Film Thickness Measurement

ABSTRACTTwo techniques for thin film measurement were compared: an optical method combining ellipsometry and reflectance spectroscopy, and cross-sectional transmission electron microscopy. These techniques were used to measure the absolute thicknesses of titania/silica sol-gel films in the size range 0.1 to 0.8 microns. The relative advantages and disadvantages of these methods will be described in this study.

Application of EDS Technique for OSP Film Thickness Measurement

2006 ◽  
Author(s):  
Prong Kongsubto ◽  
Sirarat Kongwudthiti
Keyword(s):  
Thin Film ◽  
Quantitative Analysis ◽  
Joint Strength ◽  
Critical Factor ◽  
Thickness Measurement ◽  
Ic Manufacturing ◽  
And Control ◽  
Film Thickness Measurement ◽  
Non Destructive

Abstract Organic solderability preservatives (OSPs) pad is one of the pad finishing technologies where Cu pad is coated with a thin film of an organic material to protect Cu from oxidation during storage and many processes in IC manufacturing. Thickness of OSP film is a critical factor that we have to consider and control in order to achieve desirable joint strength. Until now, no non-destructive technique has been proposed to measure OSP thickness on substrate. This paper reports about the development of EDS technique for estimating OSP thickness, starting with determination of the EDS parameter followed by establishing the correlation between C/Cu ratio and OSP thickness and, finally, evaluating the accuracy of the EDS technique for OSP thickness measurement. EDS quantitative analysis was proved that it can be utilized for OSP thickness estimation.

Transistors with a Profiled Active Layer Made by Hot-Wire Cvd

1998 ◽  
Vol 507 ◽  
Author(s):  
H. Meiling ◽  
A.M. Brockhoff ◽  
J.K. Rath ◽  
R.E.I. Schropp
Keyword(s):  
Thin Film ◽  
Active Layer ◽  
Hot Wire ◽  
Semiconductor Interface ◽  
Cross Sectional ◽  
Silicon Matrix ◽  
Bias Stress ◽  
Silicon Devices ◽  
Transmission Electron ◽  
Conducting Research

ABSTRACTIn order to obtain stable thin-film silicon devices we are conducting research on the implementation of hot-wire CVD amorphous and polycrystalline silicon in thin-film transistors, TFFs. We present results on TFTs with a profiled active layer (deposited at ≥9 Å/s), and correlate the electrical properties with the structure of the silicon matrix at the insulator/semiconductor interface, as determined with cross-sectional transmission electron microscopy. Devices prepared with an appropriate H2 dilution of SiH4 show cone-shaped crystalline inclusions. These crystals start at the interface in some cases, and in others exhibit an 80nm incubation layer prior to nucleation. The crystals in the TFTs with the incubation layer are not cone-shaped, but are rounded off. The hot-wire CVD deposited devices exhibit a high fieldeffect mobility up to 1.5 cm2V−1s−l. Also, these devices have superior stability upon continuous gate bias stress, as compared to conventional glow-discharge α-Si:H TFTs. We ascribe this to a combination of enhanced structural order of the silicon and a low hydrogen content.

Sign in / Sign up

Export Citation Format

Share Document