The Effect of Annealing on the Structure of Epitaxial CaF2 Films on Si(100)

1989 ◽  
Vol 148 ◽  
Author(s):  
Julia M. Phillips ◽  
J. E. Palmer ◽  
N. E. Hecker ◽  
C. V. Thompson
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Annealing Conditions

ABSTRACTWe have studied the effect of different annealing conditions on the crystallinity and morphology of 1000Å epitaxial CaF2 films on Si(100). The crystallinity of the films is improved by the anneals, with the highest anneal temperatures giving the greatest improvement. The results are consistent with the model previously proposed to explain the success of rapid thermal annealing in improving thicker epitaxial CaF2 films.

Correlation Between Defect Characteristics and Layer Intermixing in Si Implanted GaAs/AIGaAs Superlattices

1989 ◽  
Vol 147 ◽  
Author(s):  
Samuel Chen ◽  
S.-Tong Lee ◽  
G. Braunstein ◽  
G. Rajeswaran ◽  
P. Fellinger
Keyword(s):  
Ion Implantation ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Peak Position ◽  
Compound Semiconductor ◽  
Subsequent Annealing ◽  
Semiconductor Superlattices ◽  
Furnace Annealing ◽  
Annealing Conditions ◽  
Induced Defects

AbstractDefects induced by ion implantation and subsequent annealing are found to either promote or suppress layer intermixing in Ill-V compound semiconductor superlattices (SLs). We have studied this intriguing relationship by examining how implantation and annealing conditions affect defect creation and their relevance to intermixing. Layer intermixing has been induced in SLs implanted with 220 keV Si+ at doses < 1 × 1014 ions/cm2 and annealed at 850°C for 3 hrs or 1050°C for 10 s. Upon furnace annealing, significant Si in-diffusion is observed over the entire intermixed region, but with rapid thermal annealing layer intermixing is accompanied by negligible Si movement. TEM showed that the totally intermixed layers are centered around a buried band of secondary defects and below the Si peak position. In the nearsurface region layer intermixing is suppressed and is only partially completed at ≤1 × 1015 Si/cm2. This inhibition is correlated to a loss of the mobile implantation-induced defects, which are responsible for intermixing.

Recrystallization of Implanted LPCVD Amorphous Si Films Using Rapid Thermal Annealing

1986 ◽  
Vol 74 ◽  
Author(s):  
R. Kwor ◽  
S. M. Tang ◽  
N. S. Alvi
Keyword(s):  
Electron Microscopy ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Dwell Time ◽  
Hall Effect Measurement ◽  
Temperature Coefficient Of Resistance ◽  
Annealing Conditions ◽  
Transmission Electron ◽  
Amorphous Si ◽  
Si Films

AbstractThe effect of rapid thermal annealing on the crystallization of arsenic and boron implanted amorphous silicon films is studied. Amorphous Si films of 4000 Å were deposited using LPCVD and implanted with arsenic or boron to doses of 5 × 1013, 5 × 1014, and 5 × 1015 cm−2. These films were then annealed using an Eaton Nova-400 RTA system (with temperature ranging from 900 to 1200 °C and dwell time ranging from 1 to 30 sec). The annealed films were studied using transmission electron microscopy, Hall effect measurement and temperature coefficient of resistance measurement. The optimal annealing conditions for the films were found.

Shallow Junctions for Sub-100 Nm Cmos Technology

2001 ◽  
Vol 669 ◽  
Author(s):  
Veerle Meyssen ◽  
Peter Stolk ◽  
Jeroen van Zijl ◽  
Jurgen van Berkum ◽  
Willem van de Wijgert ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Cmos Technology ◽  
Low Energy ◽  
Annealing Conditions ◽  
Delta Doping ◽  
Shallow Junctions ◽  
P Type ◽  
Spike Annealing

ABSTRACTThis paper studies the use of ion implantation and rapid thermal annealing for the fabrication of shallow junctions in sub-100 nm CMOS technology. Spike annealing recipes were optimized on the basis of delta-doping diffusion experiments and shallow junction characteristics. In addition, using GeF2 pre-amorphization implants in combination with low-energy BF2 and spike annealing, p-type junctions depths of 30 nm were obtained with sheet resistances as low as 390 Ω/sq. The combined finetuning of implantation and annealing conditions is expected to enable junction scaling into the 70-nm CMOS technology node.

Effect of Rapid Thermal Annealing Conditions on Parameters of Ni/21R-SiC Contacts

2002 ◽  
Vol 389-393 ◽  
pp. 905-908 ◽  
Author(s):  
V.L. Litvinov ◽  
K.D. Demakov ◽  
Oleg A. Agueev ◽  
Alexander M. Svetlichnyi ◽  
Raisa V. Konakova ◽  
...  
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Annealing Conditions
Sign in / Sign up

Export Citation Format

Share Document