Processing Simox Wafer Below the Critical Temperature

1987 ◽  
Vol 107 ◽  
Author(s):  
Piran Sioshansi ◽  
Fereydoon Namavar

AbstractThe creation of SIMOX material by multiple step substoichiometry oxygen ion implantation of silicon wafers followed by high temperature annealing has already been demonstrated by different groups [1-4] This paper reports on the formation of SIMOX wafers at temperatures well below the critical temperature (500-550°C) specified for oxygen implantation of the SIMOX process. A multiple step procedure has been devised, each step consisting of oxygen ion implantation at doses of 2.5 and 3 x 1017 O+/cm2 followed by solid phase epitaxy at a temperature of 950°C for two hours. Non-destructive optical analysis and XTEM investigation of the wafers indicates the formation of a continuous buried oxide with good quality single crystal silicon on the surface after accumulated dose of 1.1x1018 O+/cm2 following high temperature annealing at 1300°C for six hours.The processing of SIMOX material at a lower temperature will enable the utilization of a wide variety of ion implanters, will simplify the design of the end station of the new generation high current ion implanters, and will have an impact on the availability and economics of SIMOX wafers.

Author(s):  
N. Lewis ◽  
E. L. Hall ◽  
A. Mogro-Campero ◽  
R. P. Love

The formation of buried oxide structures in single crystal silicon by high-dose oxygen ion implantation has received considerable attention recently for applications in advanced electronic device fabrication. This process is performed in a vacuum, and under the proper implantation conditions results in a silicon-on-insulator (SOI) structure with a top single crystal silicon layer on an amorphous silicon dioxide layer. The top Si layer has the same orientation as the silicon substrate. The quality of the outermost portion of the Si top layer is important in device fabrication since it either can be used directly to build devices, or epitaxial Si may be grown on this layer. Therefore, careful characterization of the results of the ion implantation process is essential.


1984 ◽  
Vol 37 ◽  
Author(s):  
John C. Bravman ◽  
Gary L. Patton ◽  
Robert Sinclair ◽  
James D. Plummer

AbstractUsing high resolution lattice imaging techniques, the morphology of thepolycrystalline silicon - single crystal silicon interface has been correlated to (1) the surface treatment used prior to polysilicon deposition, (2) the polysilicon implant dose, and (3) high temperature annealing. Specimens which were chemically oxidized prior to deposition exhibited a continuous layer of amorphous oxide ≈1.5nm thick. High temperature annealing produces small discontinuities in this oxide which allow the polysilicon to make direct contact with, and become epitaxially aligned to, the substrate. Specimens which were etched in HF prior to deposition were characterized by nearly oxide-free interfaces, which, following implantation and annealing, exhibited regions of epitaxial realignment significantly larger than those found in the chemically oxidized films. Heavily implanted films annealed at high temperature displayed almost complete epitaxial realignment.


Author(s):  
Н.А. Соболев ◽  
О.В. Александров ◽  
В.И. Сахаров ◽  
И.Т. Серенков ◽  
Е.И. Шек ◽  
...  

AbstractThe implantation of Czochralski-grown p -type silicon with 1-MeV germanium ions at a dose of 2 . 5 × 10^14 cm^–2 does not lead to the amorphization of single-crystal silicon. Under subsequent high-temperature annealing, electrically active acceptor centers are transformed. Their concentration and special distribution depend on the annealing temperature. The possible factors determining how these centers are formed are discussed.


Author(s):  
N. David Theodore ◽  
Leslie H. Allen ◽  
C. Barry Carter ◽  
James W. Mayer

Metal/polysilicon investigations contribute to an understanding of issues relevant to the stability of electrical contacts in semiconductor devices. These investigations also contribute to an understanding of Si lateral solid-phase epitactic growth. Metals such as Au, Al and Ag form eutectics with Si. reactions in these metal/polysilicon systems lead to the formation of large-grain silicon. Of these systems, the Al/polysilicon system has been most extensively studied. In this study, the behavior upon thermal annealing of Au/polysilicon bilayers is investigated using cross-section transmission electron microscopy (XTEM). The unique feature of this system is that silicon grain-growth occurs at particularly low temperatures ∽300°C).Gold/polysilicon bilayers were fabricated on thermally oxidized single-crystal silicon substrates. Lowpressure chemical vapor deposition (LPCVD) at 620°C was used to obtain 100 to 400 nm polysilicon films. The surface of the polysilicon was cleaned with a buffered hydrofluoric acid solution. Gold was then thermally evaporated onto the samples.


2000 ◽  
Vol 622 ◽  
Author(s):  
Liang-Yu Chen ◽  
Gary W. Hunter ◽  
Philip G. Neudeck

ABSTRACTSingle crystal silicon carbide (SiC) has such excellent physical, chemical, and electronic properties that SiC based semiconductor electronics can operate at temperatures in excess of 600°C well beyond the high temperature limit for Si based semiconductor devices. SiC semiconductor devices have been demonstrated to be operable at temperatures as high as 600°C, but only in a probe-station environment partially because suitable packaging technology for high temperature (500°C and beyond) devices is still in development. One of the core technologies necessary for high temperature electronic packaging is semiconductor die-attach with low and stable electrical resistance. This paper discusses a low resistance die-attach method and the results of testing carried out at both room temperature and 500°C in air. A 1 mm2 SiC Schottky diode die was attached to aluminum nitride (AlN) and 96% pure alumina ceramic substrates using precious metal based thick-film material. The attached test die using this scheme survived both electronically and mechanically performance and stability tests at 500°C in oxidizing environment of air for 550 hours. The upper limit of electrical resistance of the die-attach interface estimated by forward I-V curves of an attached diode before and during heat treatment indicated stable and low attach-resistance at both room-temperature and 500°C over the entire 550 hours test period. The future durability tests are also discussed.


Author(s):  
S. A. Vabishchevich ◽  
S. D. Brinkevich ◽  
V. S. Prosolovich ◽  
N. V. Vabishchevich ◽  
D. I. Brinkevich

2013 ◽  
Vol 529 ◽  
pp. 407-411 ◽  
Author(s):  
Ying Zhao ◽  
Guosong Wu ◽  
Qiuyuan Lu ◽  
Jun Wu ◽  
Ruizhen Xu ◽  
...  

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