Evidence and Characterization of Crystallographic Defect and Material Quality after SLIM-Cut Process

2011 ◽  
Vol 1323 ◽  
Author(s):  
Alex Masolin ◽  
Jan Vaes ◽  
Frederic Dross ◽  
Roberto Martini ◽  
Amaia Pesquera Rodriguez ◽  
...  
Keyword(s):  
Defect Density ◽  
Negative Impact ◽  
Deep Level ◽  
Silicon Substrates ◽  
Crystallographic Defect ◽  
Transient Spectroscopy ◽  
Electronic Activity ◽  
Crystallographic Defects

ABSTRACTThe SLIM-Cut process is a kerf-free wafering technique to obtain silicon substrates as thin as 50μm. The quality of the resulting material must be assessed to ensure that this innovative Si-foil approach does not jeopardize the potential efficiency of the final solar cell in terms of electronic activity, defect density and location. For that reason, we performed Microwave-Detected Photoconductance Decay (MW-PCD), Deep-Level Transient Spectroscopy (DLTS) and optical inspections after defect etching of the foils surface. Analyses indicate that SLIM-Cut generates crystallographic defects which create deep level traps that have a negative impact on the lifetime of the silicon foil. Nonetheless, a decrease of the thermal budget will lead to a reduction of plasticity and hence lower the amount of defects and increase the foil quality.

Low-Pressure Fast Growth and Characterization of 4H-SiC Epilayers

2010 ◽  
Vol 645-648 ◽  
pp. 77-82 ◽  
Author(s):  
Hidekazu Tsuchida ◽  
Masahiko Ito ◽  
Isaho Kamata ◽  
Masahiro Nagano ◽  
Tetsuya Miyazawa ◽  
...  
Keyword(s):  
Room Temperature ◽  
Deep Level ◽  
Fast Growth ◽  
Extended Defects ◽  
System Pressure ◽  
Transient Spectroscopy ◽  
Annealing Method ◽  
Fast Growth Rate

Fast and thick 4H-SiC epitaxial growth is demonstrated in a vertical-type reactor under a low system pressure within the range 13-40 mbar. A very fast growth rate of up to 250 m/h is obtained. The material quality of the epilayers grown in the reactor is evaluated by low-temperature photoluminescence, deep level transient spectroscopy, microwave photoconductive decay, synchrotron topography and room temperature PL imaging. The carrier lifetime of thick epilayers with or without the application of the C+-implantation/annealing method and extended defects in the epilayers grown on 8º and 4º off substrates are discussed.

Spectrum of Defect States in Porous Organic Low-k Dielectric Films, Annealed in Argon and Nitrogen

2003 ◽  
Vol 766 ◽  
Author(s):  
V. Ligatchev ◽  
T.K.S. Wong ◽  
T.K. Goh ◽  
Rusli Suzhu Yu
Keyword(s):  
Deep Level ◽  
Dielectric Films ◽  
Silicon Substrates ◽  
Reverse Bias Voltage ◽  
Defect States ◽  
Single Side ◽  
Sandwich Type ◽  
Transient Spectroscopy ◽  
P Type ◽  
Spectrum Deconvolution

AbstractDefect spectrum N(E) of porous organic dielectric (POD) films is studied with capacitance deep-level-transient-spectroscopy (C-DLTS) in the energy range up to 0.7 eV below conduction band bottom Ec. The POD films were prepared by spin coating onto 200mm p-type (1 – 10 Δcm) single-side polished silicon substrates followed by baking at 325°C on a hot plate and curing at 425°C in furnace. The film thickness is in the 5000 – 6000 Å range. The ‘sandwich’ -type NiCr/POD/p-Si/NiCr test structures showed both rectifying DC current-voltage characteristics and linear 1/C2 vs. DC reverse bias voltage. These confirm the applicability of the C-DLTS technique for defect spectrum deconvolution and the n-type conductivity of the studied films. Isochronal annealing (30 min in argon or 60 min in nitrogen) has been performed over the temperature range 300°C - 650°C. The N(E) distribution is only slightly affected by annealing in argon. However, the distribution depends strongly on the annealing temperature in nitrogen ambient. A strong N(E) peak at Ec – E = 0.55 – 0.60 eV is detected in all samples annealed in argon but this peak is practically absent in samples annealed in nitrogen at Ta < 480°C. On the other hand, two new peaks at Ec – E = 0.12 and 0.20 eV appear in the N(E) spectrum of the samples annealed in nitrogen at Ta = 650°C. The different features of the defect spectrum are attributed to different interactions of argon and nitrogen with dangling carbon bonds on the intra-pore surfaces.

Deep level transient spectroscopy characterization of InAs self-assembled quantum dots

2001 ◽  
Vol 89 (2) ◽  
pp. 1172-1174 ◽  
Author(s):  
V. V. Ilchenko ◽  
S. D. Lin ◽  
C. P. Lee ◽  
O. V. Tretyak
Keyword(s):  
Quantum Dots ◽  
Deep Level Transient Spectroscopy ◽  
Deep Level ◽  
Self Assembled ◽  
Transient Spectroscopy

Capacitance-voltage and deep-level-transient spectroscopy characterization of defects near SiO2/SiC interfaces

2011 ◽  
Vol 109 (6) ◽  
pp. 064514 ◽  
Author(s):  
A. F. Basile ◽  
J. Rozen ◽  
J. R. Williams ◽  
L. C. Feldman ◽  
P. M. Mooney
Keyword(s):  
Deep Level Transient Spectroscopy ◽  
Deep Level ◽  
Capacitance Voltage ◽  
Transient Spectroscopy

Electrical Characterization of Low Temperature PECVD Oxides for TSV Applications

2018 ◽  
Vol 2018 (1) ◽  
pp. 000728-000733
Author(s):  
Piotr Mackowiak ◽  
Rachid Abdallah ◽  
Martin Wilke ◽  
Jash Patel ◽  
Huma Ashraf ◽  
...  
Keyword(s):  
Low Temperature ◽  
Electrical Characterization ◽  
Chemical Vapor ◽  
Silicon Substrates ◽  
Low Temperature Plasma ◽  
Temperature Plasma ◽  
Charge Densities ◽  
Doped Silicon

Abstract In the present work we investigate the quality of low temperature Plasma Enhanced Chemical Vapor Deposition (PECVD) and plasma treated Tetraethyl orthosilicate (TEOS)-based TSV-liner films. Different designs of Trough Silicon Via (TSV) Test structures with 10μm and 20μm width and a depth of 100μm have been fabricated. Two differently doped silicon substrates have been used – highly p-doped and moderately doped. The results for break-through, resistivity and capacitance for the 20μm structures show a better performance compared to the 10μm structures. This is mainly due to increased liner thickness in the reduced aspect ratio case. Lower interface traps and oxide charge densities have been observed in the C-V measurements results for the 10μm structures.

Improved SiO2/ 4H-SiC Interface Defect Density Using Forming Gas Annealing

2019 ◽  
Vol 963 ◽  
pp. 465-468
Author(s):  
Stephan Wirths ◽  
Giovanni Alfieri ◽  
Alyssa Prasmusinto ◽  
Andrei Mihaila ◽  
Lukas Kranz ◽  
...  
Keyword(s):  
Defect Density ◽  
Deep Level ◽  
Flat Band ◽  
Temperature Dependent ◽  
Mos Capacitors ◽  
Interface Defect ◽  
Before And After ◽  
Oxide Deposition ◽  
Transient Spectroscopy ◽  
Post Deposition

We investigated the influence of forming gas annealing (FGA) before and after oxide deposition on the SiO2/4H-SiC interface defect density (Dit). For MOS capacitors (MOSCAPs) that were processed using FGAs at temperatures above 1050°C, CV characterization revealed decreased flat band voltage shifts and stretch-out for different sweep directions and frequencies. Moreover, constant-capacitance deep level transient spectroscopy (CC-DLTS) was performed and showed Dit levels below 1012 cm-2eV-1 for post deposition FGA at 1200°C. Finally, lateral MOSFETs were fabricated to analyze the temperature-dependent threshold voltage (Vth) shift.

Sign in / Sign up

Export Citation Format

Share Document