scholarly journals FPGA Hardware Acceleration for Visualization with Use of the Ray Tracing Algorithm

2014 ◽  
Vol 14 (2) ◽  
pp. 3-7 ◽  
Author(s):  
Liberios VOKOROKOS ◽  
Branislav MADOŠ ◽  
Viktor RUSKA
Keyword(s):  
Ray Tracing ◽  
Hardware Acceleration ◽  
Tracing Algorithm

scholarly journals Examination of the Nvidia RTX

2019 ◽  
Author(s):  
Вадим Санжаров ◽  
Vadim Sanzharov ◽  
Алексей Горбоносов ◽  
Alexey Gorbonosov ◽  
Владимир Фролов ◽  
...  
Keyword(s):  
Ray Tracing ◽  
Hardware Implementation ◽  
Hardware Acceleration ◽  
Research Field ◽  
The Public ◽  
Path Tracing ◽  
Tracing Algorithm ◽  
Active Research ◽  
Internal Architecture

Hardware acceleration of ray tracing is an active research field, but only with the release of Nvidia Turing architecture GPUs it became widely available. Nvidia RTX is a proprietary hardware ray tracing acceleration technology available in Vulkan and DirectX APIs as well as through Nvidia OptiX. Since the implementation details are unknown to the public, there are a lot of questions about what it actually does under the hood. To find answers to these questions, we implemented classic path tracing algorithm using RTX via both DirectX and Vulkan and conducted several experiments with it to investigate the inner workings of this technology. We tested actual hardware implementation of RTX technology on RTX2070 GPU and the software fallback in the driver on GTX1070 GPU. In this paper we present results of these experiments and speculate on the internal architecture of RTX.

scholarly journals Correction to: Parallel optimization of the ray-tracing algorithm based on the HPM model

2021 ◽  
Author(s):  
Wang Jun-Feng ◽  
Ding Gang-Yi ◽  
Wang Yi-Ou ◽  
Li Yu-Gang ◽  
Zhang Fu-Quan
Keyword(s):  
Ray Tracing ◽  
Parallel Optimization ◽  
Tracing Algorithm

Hardware-Accelerated Dual-Split Trees

2020 ◽  
Vol 3 (2) ◽  
pp. 1-21
Author(s):  
Daqi Lin ◽  
Elena Vasiou ◽  
Cem Yuksel ◽  
Daniel Kopta ◽  
Erik Brunvand
Keyword(s):  
Ray Tracing ◽  
Hardware Acceleration ◽  
Memory Storage ◽  
Compact Representation ◽  
Space Partitioning ◽  
Data Movement ◽  
Bounding Volume ◽  
Bounding Boxes ◽  
Split Trees ◽  
Bounding Volume Hierarchies

Bounding volume hierarchies (BVH) are the most widely used acceleration structures for ray tracing due to their high construction and traversal performance. However, the bounding planes shared between parent and children bounding boxes is an inherent storage redundancy that limits further improvement in performance due to the memory cost of reading these redundant planes. Dual-split trees can create identical space partitioning as BVHs, but in a compact form using less memory by eliminating the redundancies of the BVH structure representation. This reduction in memory storage and data movement translates to faster ray traversal and better energy efficiency. Yet, the performance benefits of dual-split trees are undermined by the processing required to extract the necessary information from their compact representation. This involves bit manipulations and branching instructions which are inefficient in software. We introduce hardware acceleration for dual-split trees and show that the performance advantages over BVHs are emphasized in a hardware ray tracing context that can take advantage of such acceleration. We provide details on how the operations needed for decoding dual-split tree nodes can be implemented in hardware and present experiments in a number of scenes with different sizes using path tracing. In our experiments, we have observed up to 31% reduction in render time and 38% energy saving using dual-split trees as compared to binary BVHs representing identical space partitioning.

Uncertainties evaluations in the ray-tracing algorithm based on Monte Carlo method

2014 ◽  
Author(s):  
Guojin Feng ◽  
Ping Li ◽  
Yingwei He ◽  
Yu Wang ◽  
Houping Wu
Keyword(s):  
Monte Carlo ◽  
Monte Carlo Method ◽  
Ray Tracing ◽  
Tracing Algorithm
Sign in / Sign up

Export Citation Format

Share Document