scholarly journals Reproducible floating-point atomic addition in data-parallel environment

2015 ◽  
Author(s):  
David Defour ◽  
Sylvain Collange
Keyword(s):  
Floating Point ◽  
Data Parallel ◽  
Parallel Environment

scholarly journals Symbolic Crosschecking of Data-Parallel Floating-Point Code

2014 ◽  
Vol 40 (7) ◽  
pp. 710-737 ◽  
Author(s):  
Peter Collingbourne ◽  
Cristian Cadar ◽  
Paul H.J. Kelly
Keyword(s):  
Floating Point ◽  
Data Parallel ◽  
Point Code

Four Parallel Channels Radix-4 FFT with Single Floating-Point Butterfly

2013 ◽  
Vol 427-429 ◽  
pp. 708-711 ◽  
Author(s):  
Ji Yang Yu ◽  
Dan Huang ◽  
Xin Li ◽  
Ke Xu ◽  
Li Ming Guo ◽  
...  
Keyword(s):  
Real Time ◽  
Design Method ◽  
Floating Point ◽  
Efficient Design ◽  
Single Precision ◽  
Data Parallel ◽  
Time Calculation ◽  
Parallel Channels ◽  
Ip Cores ◽  
Calculation Ability

An efficient design method of four parallel channels in-order FFT with single floating-point butterfly is proposed, to reduce the resource consumption and improve the real-time calculation ability. The radix-4 FFT is deduced to calculate the access address for four channel data parallel. The hardware architecture of the proposed FFT is presented, and the single precision floating-point adder and multiplier are also depicted. The proposed architecture of a four channels 1024 points radix-4 FFT with single butterfly is implemented in FPGA, and the performance is compared with previous literatures and some EDA corporations IP cores, which shows the correctness and effectiveness of the proposed method.

CONVEYOR MODEL AND IMPLEMENTATION OF THE REAL NUMBERS ADDER ON FPGA

2020 ◽  
Vol 33 (109) ◽  
pp. 21-31
Author(s):  
І. Ya. Zeleneva ◽  
Т. V. Golub ◽  
T. S. Diachuk ◽  
А. Ye. Didenko
Keyword(s):  
Performance Improvement ◽  
Experimental Studies ◽  
Production Costs ◽  
Floating Point ◽  
Computing Device ◽  
Quartus Ii ◽  
Functional Blocks ◽  
Mental Testing ◽  
Processor Cores ◽  
Floating Point Numbers

The purpose of these studies is to develop an effective structure and internal functional blocks of a digital computing device – an adder, that performs addition and subtraction operations on floating- point numbers presented in IEEE Std 754TM-2008 format. To improve the characteristics of the adder, the circuit uses conveying, that is, division into levels, each of which performs a specific action on numbers. This allows you to perform addition / subtraction operations on several numbers at the same time, which increas- es the performance of calculations, and also makes the adder suitable for use in modern synchronous cir- cuits. Each block of the conveyor structure of the adder on FPGA is synthesized as a separate project of a digital functional unit, and thus, the overall task is divided into separate subtasks, which facilitates experi- mental testing and phased debugging of the entire device. Experimental studies were performed using EDA Quartus II. The developed circuit was modeled on FPGAs of the Stratix III and Cyclone III family. An ana- logue of the developed circuit was a functionally similar device from Altera. A comparative analysis is made and reasoned conclusions are drawn that the performance improvement is achieved due to the conveyor structure of the adder. Implementation of arithmetic over the floating-point numbers on programmable logic integrated cir- cuits, in particular on FPGA, has such advantages as flexibility of use and low production costs, and also provides the opportunity to solve problems for which there are no ready-made solutions in the form of stand- ard devices presented on the market. The developed adder has a wide scope, since most modern computing devices need to process floating-point numbers. The proposed conveyor model of the adder is quite simple to implement on the FPGA and can be an alternative to using built-in multipliers and processor cores in cases where the complex functionality of these devices is redundant for a specific task.

Floating Point Operations in PipeRench CGRA

2012 ◽  
Vol 1 (6) ◽  
pp. 67-68
Author(s):  
M. Somasekhar M. Somasekhar ◽  
Keyword(s):  
Floating Point

Data-parallel line relaxation method for the Navier-Stokes equations

AIAA Journal ◽  
1998 ◽  
Vol 36 ◽  
pp. 1603-1609 ◽  
Author(s):  
Michael J. Wright ◽  
Graham V. Candler ◽  
Deepak Bose
Keyword(s):  
Stokes Equations ◽  
Relaxation Method ◽  
Parallel Line ◽  
Navier Stokes ◽  
Navier Stokes Equations ◽  
Data Parallel
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