Fast random number generation with bandwidth-enhanced chaos and post-processing

2014 ◽  
Vol 1 ◽  
pp. 142-145
Author(s):  
Taiki Yamazaki ◽  
Yasuhiro Akizawa ◽  
Atsushi Uchida ◽  
Kazuyuki Yoshimura ◽  
Kenichi Arai ◽  
...  
Keyword(s):  
Random Number ◽  
Random Number Generation ◽  
Post Processing ◽  
Number Generation

Random Number Generation Based on the Rossler Attractor

2014 ◽  
Vol 1 ◽  
pp. 272-275 ◽  
Author(s):  
Vincent Canals ◽  
Antoni Morro ◽  
Josep L. Rosselló
Keyword(s):  
Random Number ◽  
Random Number Generation ◽  
Number Generation

On-chip tunable SOI interferometer for quantum random number generation based on phase diffusion in lasers

2021 ◽  
Vol 485 ◽  
pp. 126736
Author(s):  
Muhammad Imran ◽  
Vito Sorianello ◽  
Francesco Fresi ◽  
Bushra Jalil ◽  
Marco Romagnoli ◽  
...  
Keyword(s):  
Random Number ◽  
Random Number Generation ◽  
Phase Diffusion ◽  
Number Generation ◽  
On Chip

scholarly journals True Random Number Generator Based on Fibonacci-Galois Ring Oscillators for FPGA

2021 ◽  
Vol 11 (8) ◽  
pp. 3330
Author(s):  
Pietro Nannipieri ◽  
Stefano Di Matteo ◽  
Luca Baldanzi ◽  
Luca Crocetti ◽  
Jacopo Belli ◽  
...  
Keyword(s):  
Field Programmable Gate Array ◽  
Random Number ◽  
Random Number Generator ◽  
Random Number Generation ◽  
Galois Ring ◽  
Number Generator ◽  
True Random Number Generator ◽  
Number Generation ◽  
Field Programmable ◽  
Gate Array

Random numbers are widely employed in cryptography and security applications. If the generation process is weak, the whole chain of security can be compromised: these weaknesses could be exploited by an attacker to retrieve the information, breaking even the most robust implementation of a cipher. Due to their intrinsic close relationship with analogue parameters of the circuit, True Random Number Generators are usually tailored on specific silicon technology and are not easily scalable on programmable hardware, without affecting their entropy. On the other hand, programmable hardware and programmable System on Chip are gaining large adoption rate, also in security critical application, where high quality random number generation is mandatory. The work presented herein describes the design and the validation of a digital True Random Number Generator for cryptographically secure applications on Field Programmable Gate Array. After a preliminary study of literature and standards specifying requirements for random number generation, the design flow is illustrated, from specifications definition to the synthesis phase. Several solutions have been studied to assess their performances on a Field Programmable Gate Array device, with the aim to select the highest performance architecture. The proposed designs have been tested and validated, employing official test suites released by NIST standardization body, assessing the independence from the place and route and the randomness degree of the generated output. An architecture derived from the Fibonacci-Galois Ring Oscillator has been selected and synthesized on Intel Stratix IV, supporting throughput up to 400 Mbps. The achieved entropy in the best configuration is greater than 0.995.

scholarly journals On speeding up stochastic simulations by parallelization of random number generation

2015 ◽  
Vol 137 ◽  
pp. 828-836 ◽  
Author(s):  
Che-Chi Shu ◽  
Vu Tran ◽  
Jeremy Binagia ◽  
Doraiswami Ramkrishna
Keyword(s):  
Random Number ◽  
Random Number Generation ◽  
Stochastic Simulations ◽  
Number Generation
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