Interlaboratory Study of Adhesion Using Voltage Contrast XPS

2009 ◽  
pp. 92-92-11
Author(s):  
JD Miller ◽  
GW Zajac ◽  
T Nguyen
Author(s):  
T.C. Sheu ◽  
S. Myhajlenko ◽  
D. Davito ◽  
J.L. Edwards ◽  
R. Roedel ◽  
...  

Liquid encapsulated Czochralski (LEC) semi-insulating (SI) GaAs has applications in integrated optics and integrated circuits. Yield and device performance is dependent on the homogeniety of the wafers. Therefore, it is important to characterise the uniformity of the GaAs substrates. In this respect, cathodoluminescence (CL) has been used to detect the presence of crystal defects and growth striations. However, when SI GaAs is examined in a scanning electron microscope (SEM), there will be a tendency for the surface to charge up. The surface charging affects the backscattered and secondary electron (SE) yield. Local variations in the surface charge will give rise to contrast (effectively voltage contrast) in the SE image. This may be associated with non-uniformities in the spatial distribution of resistivity. Wakefield et al have made use of “charging microscopy” to reveal resistivity variations across a SI GaAs wafer. In this work we report on CL imaging, the conditions used to obtain “charged” SE images and some aspects of the contrast behaviour.


PCI Journal ◽  
2020 ◽  
Vol 65 (4) ◽  
Author(s):  
Rémy D. Lequesne ◽  
William N. Collins ◽  
Enrico Lucon ◽  
David Darwin ◽  
Ashwin Poudel

Author(s):  
Lucile C. Teague Sheridan ◽  
Linda Conohan ◽  
Chong Khiam Oh

Abstract Atomic force microscopy (AFM) methods have provided a wealth of knowledge into the topographic, electrical, mechanical, magnetic, and electrochemical properties of surfaces and materials at the micro- and nanoscale over the last several decades. More specifically, the application of conductive AFM (CAFM) techniques for failure analysis can provide a simultaneous view of the conductivity and topographic properties of the patterned features. As CMOS technology progresses to smaller and smaller devices, the benefits of CAFM techniques have become apparent [1-3]. Herein, we review several cases in which CAFM has been utilized as a fault-isolation technique to detect middle of line (MOL) and front end of line (FEOL) buried defects in 20nm technologies and beyond.


Author(s):  
Fred Y. Chang ◽  
Victer Chan

Abstract This paper describes a novel de-process flow by combining cobalt silicide / nitride wet etch with KOH electrochemical wet etch (ECW) to identify leaky gate in silicided deep sub-micron process technology. Traditionally, leaky gate identification requires direct confirmation by gate level electrical or emission detection technique. Ohtani [1] used KOH electrochemical etch application to identify nonsilicided leaky gate capacitor in DRAM without using the above confirmation. The result of the case study demonstrates the expanded application of ECW etch to both silicided 0.18um logic and SRAM devices. Voltage contrast at metal 1 to assist leaky gate localization is also proposed. By combining both techniques, the possibility for isolating gate related defects are greatly enhanced. Case studies also show the advantages of the proposed technique over conventional poly level voltage contrast in leaky gate identification especially with devices that use local interconnect and nitride liner process.


Author(s):  
Natsuko Asano ◽  
Shunsuke Asahina ◽  
Natasha Erdman

Abstract Voltage contrast (VC) observation using a scanning electron microscope (SEM) or a focused ion beam (FIB) is a common failure analysis technique for semiconductor devices.[1] The VC information allows understanding of failure localization issues. In general, VC images are acquired using secondary electrons (SEs) from a sample surface at an acceleration voltage of 0.8–2.0 kV in SEM. In this study, we aimed to find an optimized electron energy range for VC acquisition using Auger electron spectroscopy (AES) for quantitative understanding.


Author(s):  
Oliver D. Patterson ◽  
Deborah A. Ryan ◽  
Xiaohu Tang ◽  
Shuen Cheng Lei

Abstract In-line E-beam inspection may be used for rapid generation of failure analysis (FA) results for low yielding test structures. This approach provides a number of advantages: 1) It is much earlier than traditional FA, 2) de-processing isn’t required, and 3) a high volume of sites can be processed with the additional support of an in-line FIB. Both physical defect detection and voltage contrast inspection modes are useful for this application. Voltage contrast mode is necessary for isolation of buried defects and is the preferred approach for opens, because it is faster. Physical defect detection mode is generally necessary to locate shorts. The considerations in applying these inspection modes for rapid failure analysis are discussed in the context of two examples: one that lends itself to physical defect inspection and the other, more appropriately addressed with voltage contrast inspection.


Author(s):  
Jon C. Lee ◽  
J. H. Chuang

Abstract As integrated circuits (IC) have become more complicated with device features shrinking into the deep sub-micron range, so the challenge of defect isolation has become more difficult. Many failure analysis (FA) techniques using optical/electron beam and scanning probe microscopy (SPM) have been developed to improve the capability of defect isolation. SPM provides topographic imaging coupled with a variety of material characterization information such as thermal, magnetic, electric, capacitance, resistance and current with nano-meter scale resolution. Conductive atomic force microscopy (C-AFM) has been widely used for electrical characterization of dielectric film and gate oxide integrity (GOI). In this work, C-AFM has been successfully employed to isolate defects in the contact level and to discriminate various contact types. The current mapping of C-AFM has the potential to identify micro-leaky contacts better than voltage contrast (VC) imaging in SEM. It also provides I/V information that is helpful to diagnose the failure mechanism by comparing I/V curves of different contact types. C-AFM is able to localize faulty contacts with pico-amp current range and to characterize failure with nano-meter scale lateral resolution. C-AFM should become an important technique for IC fault localization. FA examples of this technique will be discussed in the article.


Author(s):  
Michael B. Schmidt ◽  
Noor Jehan Saujauddin

Abstract Scan testing and passive voltage contrast (PVC) techniques have been widely used as failure analysis fault isolation tools. Scan diagnosis can narrow a failure to a given net and passive voltage contrast can give real-time, large-scale electronic information about a sample at various stages of deprocessing. In the highly competitive and challenging environment of today, failure analysis cycle time is very important. By combining scan FA with a much higher sensitivity passive voltage contrast technique, one can quickly find defects that have traditionally posed a great challenge.


Author(s):  
Jong Hak Lee ◽  
Jong Eun Kim ◽  
Chang Su Park ◽  
Nam Il Kim ◽  
Jang Won Moon ◽  
...  

Abstract In this work, a slightly unetched gate hard mask failure was analyzed by nano probing. Although unetched hard mask failures are commonly detected from the cross sectional view with FIB or FIB-TEM and planar view with the voltage contrast, in this case of the very slightly unetched hard mask, it was difficult to find the defects within the failed area by physical analysis methods. FIB is useful due to its function of milling and checking from the one region to another region within the suspected area, but the defect, located under contact was very tiny. So, it could not be detected in the tilted-view of the FIB. However, the state of the failure could be understood from the electrical analysis using a nano probe due to its ability to probe contact nodes across the fail area. Among the transistors in the fail area, one transistor’s characteristics showed higher leakage current and lower ON current than expected. After physical analysis, slightly remained hard mask was detected by TEM. Chemical processing was followed to determine the gate electrode (WSi2) connection to tungsten contact. It was also proven that when gate is floated, more leakage current flows compared to the state that the zero voltage is applied to the gate. This was not verified by circuit simulation due to the floating nodes.


Author(s):  
Wei-Chih Wang ◽  
Jian-Shing Luo

Abstract In this paper, we revealed p+/n-well and n+/p-well junction characteristic changes caused by electron beam (EB) irradiation. Most importantly, we found a device contact side junction characteristic is relatively sensitive to EB irradiation than its whole device characteristic; an order of magnitude excess current appears at low forward bias region after 1kV EB acceleration voltage irradiation (Vacc). Furthermore, these changes were well interpreted by our Monte Carlo simulation results, the Shockley-Read Hall (SRH) model and the Generation-Recombination (G-R) center trap theory. In addition, four essential examining items were suggested and proposed for EB irradiation damage origins investigation and evaluation. Finally, by taking advantage of the excess current phenomenon, a scanning electron microscope (SEM) passive voltage contrast (PVC) fault localization application at n-FET region was also demonstrated.


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