Test Method for Measuring Warp and Total Thickness Variation on Silicon Wafers by Noncontact Scanning

10.1520/f0657 ◽  
2003 ◽  
Author(s):  
Keyword(s):  
Silicon Wafers ◽  
Test Method ◽  
Thickness Variation ◽  
Total Thickness ◽  
Total Thickness Variation

Production Proven, High Precision Temporary Bond/De-bond Process

2013 ◽  
Vol 2013 (1) ◽  
pp. 000861-000865 ◽  
Author(s):  
Blake Dronen ◽  
Aric Shorey ◽  
B.K. Wang ◽  
Leon Tsai
Keyword(s):  
High Precision ◽  
Support System ◽  
Thickness Variation ◽  
Total Thickness ◽  
Critical Step ◽  
Low Coherence ◽  
Total Thickness Variation ◽  
Thinning Operations ◽  
Wafer Thinning

Wafer thinning represents a critical step in 2.5D and 3D-IC integration. Achieving low total thickness variation (TTV) of a bonded stack is essential since it directly impacts the TTV of the thinned device wafer. It is essential to understand and utilize appropriate processes and materials that provide precision bonded stacks prior to thinning operations in order to achieve high process yields. The 3M™ Wafer Support System and Corning's precision glass carrier wafers were used to produce bonded stacks. Leveraging metrology tools like the Flatmaster MSP-300 and low coherence interferometric probes allow for characterization of the TTV of each layer of a bonded stack and better understanding of the stack-up as well as how to minimize stack TTV. The ability to deliver stack TTV of < 2 um in a repeatable manner has been demonstrated.

Effect of Double Sided Process Parameters in Lapping Silicon Wafer

2013 ◽  
Vol 393 ◽  
pp. 259-265 ◽  
Author(s):  
Abdul Rahim Mahamad Sahab ◽  
Nor Hayati Saad ◽  
Amirul Abdul Rashid ◽  
Yusoff Noriah ◽  
Nassya Mohd Said ◽  
...  
Keyword(s):  
Silicon Wafer ◽  
Process Parameters ◽  
Integrated Circuit ◽  
Quality Standard ◽  
Wafer Surface ◽  
Thickness Variation ◽  
Total Thickness ◽  
Hard And Brittle Material ◽  
Total Thickness Variation ◽  
Lapping Machine

Silicon wafer is widely used in semiconductor industries for development of sensors and integrated circuit in computer, cell phones and wide variety of other devices. Demand on the device performance requires flatter wafer surface, and less dimensional wafer variation. Prime silicon wafer is hard and brittle material. Due to its properties, double sided lapping machine with ceramic grinding agent were introduced for machining high quality standard silicon wafers. The main focus is the silicon wafer with high accuracy of flatness; to reduce total thickness variation, waviness and roughness. In this paper the lapping experiment and analysis showed that the double sided lapping machine is able to produce total thickness variation less than 10 um at controlled process parameters within short processing time. Machining using low mode method reduced the total thickness variation (TTV) value. The lapping load and speed directly reflected the performance and condition of final silicon wafer quality.

A Multistep Process for Thinning Individual Die to sub-35 μm Thickness

2010 ◽  
Vol 7 (4) ◽  
pp. 189-196
Author(s):  
Jeffrey Thompson ◽  
Gary Tepolt ◽  
Livia Racz ◽  
C.B. Rogers ◽  
V.P. Manno ◽  
...  
Keyword(s):  
Glass Substrate ◽  
Chemical Mechanical Planarization ◽  
Thickness Variation ◽  
Total Thickness ◽  
Bulk Silicon ◽  
Wafer Level ◽  
Damage Layer ◽  
Die Stacking ◽  
Multistep Process ◽  
Total Thickness Variation

The drive toward increased packaging density relies on die stacking. In order to maximize functional density, die are generally thinned on the wafer level. However, high-cost low-volume applications may not have full wafers available. Therefore, a method to thin individual die must be developed. In this article, a detailed and reliable process for thinning die to sub35 μm is outlined. The process consists of four steps: pseudo-wafer lamination, mechanical lapping, chemical mechanical planarization (CMP), and die release. A pseudo-wafer is created by adhering die to a glass substrate. Mechanical lapping is used to remove the bulk silicon and reduce die thickness to approximately 50 μm. CMP is used to attain thicknesses of sub35 μm and remove the subsurface damage layer from the die. This process can reliably produce die thinned to sub35 μm with ± 1.5-μm total thickness variation (TTV). The die are then released from the glass substrate and are handled using a customized vacuum carrier.

scholarly journals The effect of the chuck shape on the wafer topography in back grinding of wafer with outer rim

2021 ◽  
Vol 13 (10) ◽  
pp. 168781402110504
Author(s):  
Xianglong Zhu ◽  
Weihua Yao ◽  
Xiaoguang Guo ◽  
Renke Kang ◽  
Muhammad Jawad Ahmad
Keyword(s):  
Integrated Circuits ◽  
Great Influence ◽  
Silicon Wafers ◽  
Thickness Variation ◽  
Grinding Wheel ◽  
Inclination Angles ◽  
Radial Thickness ◽  
Total Thickness Variation ◽  
Novel Method ◽  
The Mathematical Model

Back Grinding of Wafer with Outer Rim (BGWOR) is a novel method for carrier-less thinning of silicon wafers. Silicon wafers are widely used in integrated circuits (ICs). The topography of the wafer will not only directly affect the efficiency of subsequent processing of semiconductor devices, but correspondingly affect the performance and life of these devices. However, there are few studies on the shape of the ground wafer in BGWOR. In this paper, the mathematical model of the wafer topography in BGWOR was developed. With this model, the radial thickness and total thickness variation (TTV) of a wafer under different parameters, including inclination angles and radii of grinding wheel for dressing chuck, were simulated by MATLAB. Inclination angles and radii of grinding wheels for the dressing chuck had a great influence on the radial thickness and TTV of a wafer in the BGWOR. Lastly, the pilot experiments were conducted to validate the theoretical model of grinding topography and TTV of the wafer in BGWOR. To enhance the flatness of the ground wafer, it is essential to control the shape of the dressing chuck. The research results are helpful to the optimization of the dressing process of the chuck in the BGWOR.

Temporary Bonding Cost Of Ownership: The link between low total thickness variation and chip yield

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001893-001912
Author(s):  
Thomas Uhrmann ◽  
Jürgen Burggraf ◽  
Harald Wiesbauer ◽  
Julian Bravin ◽  
Thorsten Matthias ◽  
...  
Keyword(s):  
Chemical Stability ◽  
High Volume ◽  
Bonding Process ◽  
Thickness Variation ◽  
Total Thickness ◽  
Process Yield ◽  
Cost Of Ownership ◽  
Temporary Bonding ◽  
Total Thickness Variation ◽  
Determining Factor

The ability to process thin wafers with thicknesses of 20-50um on front- and backside is a key technology for 3D stacked ICs (3Ds-IC). The most obvious reason for thin wafers is the reduced form factor, which is especially important for handheld consumer devices. However, probably even more important is that thinner wafers enable significant cost reduction for TSVs. Consensus has developed on the use of Temporary Bonding / Debonding Technology as the solution of choice for reliably handling thin wafers through backside processing steps. Temporary bonding and debonding comprises several processes for which yield is essential, as costly fully functional device wafers are being processed. The presented temporary bonding process consists of a bi-layer system, a release layer, Dow Corning WL-3001 Bonding Release and an adhesive layer, Dow Corning WL-4030 or WL-4050 Bonding Adhesive, processed on EVG's 850XT universal temporary bonding and debonding platform. Furthermore, this bi-layer spin coated material allows a room temperature bonding-debonding process increase process throughput which translates to low cost of ownership for high volume manufacturing. As such, this bi-layer approach features high chemical stability exposed to phosphoric acid, nitric acid, organic solvents and other chemicals familiar to TSV fabrication. Besides chemical stability this adhesive system provides also a high thermal stability when exposed to temperatures up to 300 °C. The temporary bonding process yield has a major impact on the overall Cost of Ownership (CoO). On the other hand, throughput of the individual process steps like spin coating, bonding, cure, debonding and cleaning processes is the second determining factor for improved CoO. In this presentation, we will present a study of the total thickness variation (TTV) and the evolution of TTV at different stages of the process. High resolution in-line metrology is an enabling tool to trace the bond integrity and yield throughout backside processing. As TTV is a major determining factor of the overall process yield, understanding its impact over the bonded wafer pair carries major importance. Especially, non-continuity of the edge region, showing an inherent edge bead after coating, and edge die yield will be focus of our contribution. Finally, our experimental results will be transferred into a cost of ownership model, discussing the pros and cons for high volume production.

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